Serial Interface
M68HC12B Family Data Sheet, Rev. 9.1
198
Freescale Semiconductor
14.2.3.4 SCI Status Register 1
Read: Anytime; used in auto clearing mechanism
Write: Has no meaning or effect
The bits in these registers are set by various conditions in the SCI hardware and are cleared automatically
by special acknowledge sequences. The receive related flag bits in SC0SR1 (RDRF, IDLE, OR, NF, FE,
and PF) are all cleared by a read of the SC0SR1 register followed by a read of the transmit/receive data
register low byte. However, only those bits which were set when SC0SR1 was read will be cleared by the
subsequent read of the transmit/receive data register low byte. The transmit related bits in SC0SR1
(TDRE and TC) are cleared by a read of the SC0SR1 register followed by a write to the transmit/receive
data register low byte.
TDRE — Transmit Data Register Empty Flag
New data is not transmitted unless SC0SR1 is read before writing to the transmit data register. Reset
sets this bit.
0 = SC0DR busy
1 = Any byte in the transmit data register is transferred to the serial shift register so new data may
now be written to the transmit data register.
TC — Transmit Complete Flag
Flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
by reading SC0SR1 with TC set and then writing to SC0DR.
0 = Transmitter busy
1 = Transmitter idle
RDRF — Receive Data Register Full Flag
Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF
is set if a received character is ready to be read from SC0DR. Clear the RDRF flag by reading SC0SR1
with RDRF set and then reading SC0DR.
0 = SC0DR empty
1 = SC0DR full
IDLE — Idle Line Detected Flag
Receiver idle line is detected (the receipt of a minimum of 10 or 11 consecutive 1s). This bit is not set
by the idle line condition when the RWU bit is set. Once cleared, IDLE is not set again until after RDRF
has been set (after the line has been active and becomes idle again).
0 = RxD line active
1 = RxD line idle
Address:
$00C4
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
Write:
Reset:
1
1
0
0
0
0
0
0
= Unimplemented
Figure 14-7. SCI Status Register 1 (SC0SR1)