Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
176
Freescale Semiconductor
13.4.11 16-Bit Pulse Accumulator A Control Register
Read: Anytime
Write: Anytime
Sixteen-bit pulse accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and
PAC2. When PAEN is set, the PACA is enabled. The PACA shares the input pin with IC7.
PAEN
—
Pulse Accumulator A System Enable Bit
PAEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless
the pulse accumulator is disabled.
0 = 16-bit pulse accumulator A system disabled. Eight-bit PAC3 and PAC2 can be enabled when
their related enable bits in ICPACR ($A8) are set. Pulse accumulator input edge flag (PAIF)
function is disabled.
1 = Pulse accumulator A system enabled. The two 8-bit pulse accumulators, PAC3 and PAC2, are
cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and
PACN2 registers’ contents are, respectively, the high and low byte of the PACA. PA3EN and
PA2EN control bits in ICPACR ($A8) have no effect. Pulse accumulator input edge flag (PAIF)
function is enabled.
PAMOD
—
Pulse Accumulator Mode Bit
0 = Event counter mode
1 = Gated time accumulation mode
PEDGE
—
Pulse Accumulator Edge Control Bit
For PAMOD bit = 0, event counter mode
0 = Falling edges on PT7 pin cause the count to be incremented.
1 = Rising edges on PT7 pin cause the count to be incremented.
For PAMOD bit = 1, gated time accumulation mode
0 = PT7 input pin high enables M divided by 64 clock to pulse accumulator and the trailing falling
edge on PT7 sets the PAIF flag.
1 = PT7 input pin low enables M divided by 64 clock to pulse accumulator and the trailing rising edge
on PT7 sets the PAIF flag.
NOTE
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since
the E
÷
64 clock is generated by the timer prescaler.
Address: $00A0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-29. 16-Bit Pulse Accumulator A Control Register (PACTL)
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Pin Action
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level