Byte Data Link Communications (BDLC)
M68HC12B Family Data Sheet, Rev. 9.1
234
Freescale Semiconductor
RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and receive speed (10.4 Kbps) or receive
only at 41.6 Kbps. This feature is useful for fast downloading data into a J1850 node for diagnostic or
factory programming.
1 = BDLC is put in 4X receive-only operation.
0 = BDLC transmits and receives at 10.4 Kbps. Reception of a BREAK symbol automatically clears
this bit and sets BDLC state vector register (BSVR) to $001C.
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See
Figure 15-14
.) SAE J1850 encourages
using an active long (logic 0) for in-frame responses containing cyclical redundancy check (CRC) and
an active short (logic 1) for in-frame responses without CRC.
0 = NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR)
ends with a CRC byte. NB that is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
1 = NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR)
ends with a CRC byte. NB that is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
TEOD — Transmit End of Data Bit
This bit is set by the programmer to indicate the end of a message is being sent by the BDLC. It
appends an 8-bit CRC after completing transmission of the current byte. This bit also is used to end
an in-frame response (IFR). If the transmit shadow register is full when TEOD is set, the CRC byte is
transmitted after the current byte in the Tx shift register and the byte in the Tx shadow register have
been transmitted. (See
15.8.3 Rx and Tx Shadow Registers
for a description of the transmit shadow
register.) Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur. (See
15.9.3 BDLC State Vector
Register
.)
1 = Transmit end-of-data (EOD) symbol
0 = TEOD bit is cleared automatically at the rising edge of the first CRC bit that is sent or if an error
is detected. When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC
receives back a valid EOD symbol or an error condition occurs.
TSIFR, TMIFR1, TMIFR0 — Transmit In-Frame Response Bits
These bits control the type of in-frame response being sent. Only one of these bits should be set at a
time. If more than one are set, the priority encoding logic forces the bits to a known value as shown in
Table 15-3
. For example, if 011 is written to TSIFR, TMIFR1, and TMIFR0, then internally they are
encoded as 010. However, when these bits are read back, they read 011.
Table 15-3. Transmit In-Frame Response Bit Encoding
Write/Read
(1)
1. Shaded cells indicate bits which do not affect internal interpretation. These bits read
back as written.
Internal Interpretation
TSIFR
TMIFR1
TMIFR0
TSIFR
TMIFR1
TMIFR0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
0
1