Timer Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
169
TSWAI — Timer Module Stops While in Wait Bit
TSWAI also affects pulse accumulators and modulus down counters.
0 = Allows the timer module to continue running during wait
1 = Disables the timer module when the MCU is in wait mode. Timer interrupts cannot be used to
get the MCU out of wait.
TSBCK — Timer and Modulus Counter Stop While in Background Mode Bit
TBSCK does not stop the pulse accumulator.
0 = Allows the timer and modulus counter to continue running while in background mode
1 = Disables the timer and modulus counter whenever the MCU is in background mode. This is
useful for emulation.
TFFCA — Timer Fast Flag Clear All Bit
0 = Allows the timer flag clearing to function normally
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel
($90–$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any
access to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACN3 and
PACN2 registers ($A2, $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1).
Any access to the PACN1 and PACN0 registers ($A4, $A5) clears the PBOVF flag in the
PBFLG register ($B1). This has the advantage of eliminating software overhead in a separate
clear sequence. Extra care is required to avoid accidental flag clearing due to unintended
accesses.
13.4.7 Timer Control Registers
Read: Anytime
Write: Anytime
OMn Bits — Output Mode
OLn Bits — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare (see
Table 13-1
). When either OMn or OLn is 1, the pin associated with OCn
becomes an output tied to OCn regardless of the state of the associated DDRT bit.
NOTE
To enable output action by OMn and OLn bits on the timer port, the
corresponding bit in OC7M should be cleared.
Address: $0088
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
0
0
0
0
0
0
0
0
Figure 13-12. Timer Control Register 1 (TCTL1)
Address: $0089
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
0
0
0
0
0
0
0
0
Figure 13-13. Timer Control Register 2 (TCTL2)