参数资料
型号: MC13892JVLR2
厂商: Freescale Semiconductor
文件页数: 43/158页
文件大小: 0K
描述: IC PMU I.MX51/37/35/27 186MAPBGA
标准包装: 1,000
应用: 电池管理,显示器(LED 驱动器),手持/移动设备,电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 186-LFBGA
供应商设备封装: 186-PBGA(12x12)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
Table 10. SPI Interface Timing Specifications
Parameter
t SELSU
t SELHLD
t SELLOW
t CLKPER
t CLKHIGH
t CLKLOW
t WRTSU
t WRTHLD
t RDSU
t RDHLD
t RDEN
t RDDIS
Description
Time CS has to be high before the first rising edge of CLK
Time CS has to remain high after the last falling edge of CLK
Time CS has to remain low between two transfers
Clock period of CLK
Part of the clock period where CLK has to remain high
Part of the clock period where CLK has to remain low
Time MOSI has to be stable before the next rising edge of CLK
Time MOSI has to remain stable after the rising edge of CLK
Time MISO will be stable before the next rising edge of CLK
Time MISO will remain stable after the falling edge of CLK
Time MISO needs to become active after the rising edge of CS
Time MISO needs to become inactive after the falling edge of CS
t min (ns)
15
15
15
38
15
15
4.0
4.0
4.0
4.0
4.0
4.0
Notes
46. This table reflects a maximum SPI clock frequency of 26 MHz
Table 11. SPI Interface Logic IO Specifications
Parameter
Input Low CS, MOSI, CLK
Input High CS, MOSI, CLK
Output Low MISO, INT
Output High MISO, INT
SPIVCC Operating Range
Condition
Output sink 100 μ A
Output source 100 μ A
Min
0.0
0.7*SPIVCC
0
SPIVCC-0.2
1.75
Typ
Max
0.3*SPIVCC
SPIVCC+0.3
0.2
SPIVCC
3.1
Units
V
V
V
V
V
CL = 50 pF, SPIVCC = 1.8 V
SPIDRV[1:0] = 00 (default)
11
ns
MISO Rise and Fall Time
SPIDRV[1:0] = 01
SPIDRV[1:0] = 10
SPIDRV[1:0] = 11
6.0
High Z
22
ns
ns
ns
MC13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
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