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| 型号： | MC13892JVLR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 44/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU I.MX51/37/35/27 186MAPBGA |
| 标准包装： | 1,000 |
| 应用： | 电池管理，显示器（LED 驱动器），手持/移动设备，电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 186-LFBGA |
| 供应商设备封装： | 186-PBGA（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
I2C INTERFACE
I 2 C INTERFACE
I 2 C CONFIGURATION
When configured for I 2 C mode (see Table 7 ) the interface may be used to access the complete register map previously
described for SPI access. The MC13892 can function only as an I 2 C slave device, not as a host.
I 2 C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing
for bus conflict avoidance, pin programmable selection is provided through the MOSI pin to allow configuration for the address
LSB(s). This product supports 7-bit addressing only; support is not provided for 10-bit or General Call addressing.
The I 2 C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s
operation. Timing diagrams, electrical specifications, and further details can be found in the I 2 C specification.
Standard I 2 C protocol utilizes packets of 8-bits (bytes), with an acknowledge bit (ACK) required between each byte. However,
the number of bytes per transfer is unrestricted. The register map of the MC13892 is organized in 24-bit registers which
corresponds to the 24-bit words supported by the SPI protocol of this product. To ensure that the I 2 C operation mimics SPI
transactions in behavior of a complete 24-bit word being written in one transaction, software is expected to perform write
transactions to the device in 3 byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge
at the completion of writing the third consecutive byte.
Failure to complete a 3 byte write sequence will abort the I 2 C transaction and the register will retain its previous value. This
could be due to a premature STOP command from the master.
I 2 C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB
and 3 bytes will be sent out, unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The
host sends a master command packet after driving the start condition. The device will respond to the host if the master command
packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK
to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the
transaction.
I 2 C DEVICE ID
The I 2 C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in
addressing for bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This
product supports 7-bit addressing only. Support is not provided for 10-bit or General Call addressing.
Because the MOSI pin is not utilized for I 2 C communication, it is reassigned for pin programmable address selection by
hardwiring to VCORE or GND at the board level, when configured for I 2 C mode. MOSI will act as Bit 0 of the address. The I 2 C
address assigned to FSL PM ICs (shared amongst our portfolio) is as follows:
00010-A1-A0, where the A1 and A0 bits are allowed to be configured for either 1 or 0. It is anticipated for a maximum of two
FSL PM ICs on a given board, which could be sharing an I 2 C bus. The A1 address bit is internally hard wired as a “0”, leaving
the LSB A0 for board level configuration. The A1 bit will be implemented such that it can be re-wired as a “1” (with a metal change
or fuse trim), if conflicts are encountered before the final production material is manufactured. The designated address is defined
as: 000100-A0.
I 2 C OPERATION
The I 2 C mode of the interface is implemented, generally following the Fast mode definition, which supports up to 400 kbits/s
operation. The exceptions to the standard are noted to be 7-bit only addressing, and no support for General Call addressing.
Timing diagrams, electrical specifications, and further details can be found in the I 2 C specification, which is available for
download at:
Standard I 2 C protocol utilizes bytes of 8-bits, with an acknowledge bit (ACK) required between each byte. However, the
number of bytes per transfer are unrestricted. The register map is organized in 24-bit registers, which corresponds to the 24-bit
words supported by the SPI protocol of this product. To ensure that I 2 C operation mimics SPI transactions in behavior of a
complete 24-bit word being written in one transaction. The software is expected to perform write transactions to the device in 3
byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing
the third consecutive byte.
Failure to complete a 3 byte write sequence will abort the I 2 C transaction, and the register will retain its previous value. This
could be due to a premature STOP command from the master, for example. I 2 C read operations are also performed in byte
MC13892
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
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