- 您现在的位置：买卖IC网 > PDF目录16590 > MC13892JVLR2 (Freescale Semiconductor)IC PMU I.MX51/37/35/27 186MAPBGA PDF资料下载
参数资料
| 型号： | MC13892JVLR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 58/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU I.MX51/37/35/27 186MAPBGA |
| 标准包装： | 1,000 |
| 应用： | 电池管理，显示器（LED 驱动器），手持/移动设备，电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 186-LFBGA |
| 供应商设备封装： | 186-PBGA（12x12） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页当前第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页
FUNCTIONAL DEVICE OPERATION
OPERATING MODES
Any peripheral loading on SW4 should be isolated from the SW4 output node by the PWGT2 switch, which opens in both Low-
power off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the memory
subsystem.
Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and an the MEMHLDI interrupt
bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since
software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.
No specific timer is running in this mode.
Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when
coming out of MEMHOLD and entering a Warm Boot. The switchers will be reconfigured for their default settings as selected by
the PUMS pin in the normal time slot that would affect them.
User Off
RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled. CLK32KMCU
(connected to the processor's CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set,
or if DRM is set.
The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1, and/or SW2, and/or SW3 supply domains
can be configured for SWxUOMODE = 1 to keep them powered through the User Off event. If one of the switchers can be shut
down on in User Off, its mode bits would typically be set to 0.
Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens
in both Low-power Off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining
the processor core.
Since power is maintained for the core (which is put into its lowest power state) and since MCU RESETBMCU does not trip,
the processor's state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be
used for very low frequency / low-power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where
the system left off before the USEROFF command.
Upon a turn on event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off
will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with
external memory. No specific timer is running in this mode.
Warm Start
Entered upon a Turn On event from User Off. The switchers and regulators are powered up sequentially to limit the inrush
current; see the Power Up section for sequencing and default level details. If SW1, SW2, SW3, and/or SW4 were configured to
stay on in User Off mode, they will not be turned off when coming out of User Off and entering a Warm Start. The buck regulators
will be reconfigured for their default settings as selected by the PUMS pin in the respective time slot defined in the sequencer
selection.
RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if enabled via the SPI. The reset timer starts
running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is
generated, and RESETB will go high.
Internal MemHold Power Cut
Refer to the next section for details about Power Cuts and the associated state machine response.
POWER CUT DESCRIPTION
When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold
Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well
as the on chip memory registers and some other power control related bits. All other supplies will be disabled.
The maximum duration of a power cut is determined by the PCUT timer PCT[7:0] preset via SPI. When a PCUT occurs, the
PCUT timer will internally be decremented till it expires, meaning counted down to zero. The contents of PCT[7:0] does not reflect
the actual count down value but will keep the programmed value and therefore does not have to be reprogrammed after each
power cut.
If power is not reestablished above BPON before the PCUT timer expires, the state machine transitions to the Off mode at
expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT.
Upon re-application of power before expiration (an “successful PCUT”, defined as BP first rising above the UVDET threshold
and then above the BPON threshold before the PCUT timer expires), a Cold Start is engaged.
MC13892
Analog Integrated Circuit Device Data
58
Freescale Semiconductor
相关PDF资料 |
PDF描述 |
|---|---|
| ECM15DTAS | CONN EDGECARD 30POS R/A .156 SLD |
| GBM25DRTN-S13 | CONN EDGECARD 50POS .156 EXTEND |
| AK670M-5-R | CABLE MINI USB 4PIN 5M 1.1 VERS |
| EEM28DSXI | CONN EDGECARD 56POS DIP .156 SLD |
| MC13892JVKR2 | IC PMU I.MX51/37/35/27 139MAPBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC13892VK | 功能描述:PMIC 解决方案 PMUIC w/4 buck/12 LDO rg RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892VKR2 | 功能描述:PMIC 解决方案 PMUIC w/4 buck/12 LDO rg RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892VL | 功能描述:PMIC 解决方案 5/28V BCK/BST PMUIC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892VLR2 | 功能描述:PMIC 解决方案 5/28V BCK/BST PMUIC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC1-38RX | 制造商:3M Electronic Products Division 功能描述:NON INSL COPPER SEAMLESS RING TE 制造商:3M Electronic Products Division 功能描述:80610253439 制造商:3M Electronic Products Division 功能描述:80610253439 MC1-38RX S/LOK RING TERMINAL |
发布紧急采购，3分钟左右您将得到回复。