参数资料
型号: MC13892JVLR2
厂商: Freescale Semiconductor
文件页数: 78/158页
文件大小: 0K
描述: IC PMU I.MX51/37/35/27 186MAPBGA
标准包装: 1,000
应用: 电池管理,显示器(LED 驱动器),手持/移动设备,电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 186-LFBGA
供应商设备封装: 186-PBGA(12x12)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
SUPPLIES
100 %
90 %
80 %
70 %
S W1 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 0, 725 V
100 %
90 %
80 %
70 %
S W1 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 0, 725 V
60 %
50 %
40 %
Vin = 3 ,00 0 V
Vin = 3 ,60 0 V
Vin = 4 ,65 0 V
60 %
50 %
40 %
Vin = 3,0 00 V
Vin = 3,6 00 V
Vin = 4,6 50 V
30 %
30 %
20 %
10 %
20 %
10 %
0%
0%
0
50 1 00 150 200 25 0 300 35 0 4 00 450 50 0 55 0 6 00 650 70 0 7 50 800 85 0 90 0 9 50 10 0 1 05
0
10
20
30
40
50
60
70
80
90
10 0
0
0
100 %
90 %
80 %
70 %
Ilo a d (m A)
S W2 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 1. 250 V
100 %
90 %
80 %
70 %
Il oa d (m A)
S W2 P WM Pu lse S kip pin g m od e E ffici ency V ou t = 1.250 V
60 %
50 %
40 %
30 %
20 %
10 %
0%
Vin = 3 ,00 0 V
Vin = 3 ,60 0 V
Vin = 4 ,65 0 V
60 %
50 %
40 %
30 %
20 %
10 %
0%
Vin = 3, 000 V
Vin = 3, 600 V
Vin = 4, 650 V
0
10
20
30
40
50
60
70
80
90
10 0
0
50
1 00 1 50 20 0 25 0 300
350 4 00 4 50 50 0 55 0 600
650 7 00 7 50 80 0 85 0 900
100 %
90 %
80 %
70 %
Ilo a d (m A)
S W4 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 1. 800 V
100 %
90 %
80 %
70 %
Ilo a d (m A)
S W4 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 1. 800 V
60 %
50 %
40 %
30 %
20 %
10 %
0%
Vin = 3 ,00 0 V
Vin = 3 ,60 0 V
Vin = 4 ,65 0 V
60 %
50 %
40 %
30 %
20 %
10 %
0%
Vin = 3,0 00 V
Vin = 3,6 00 V
Vin = 4,6 50 V
0
10
20
30
40
50
60
70
80
90
10 0
0
50
1 00 1 50 20 0 2 50 30 0 35 0 400
450 5 00 5 50 60 0 65 0 700
750 8 00
850 9 00
Ilo a d (m A)
Il oa d (m A)
Figure 19. Buck Regulator PWM (Pulse Skipping) Efficiency
DYNAMIC VOLTAGE SCALING
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the
processor. SW1 and SW2 allow for three different set points with controlled transitions to avoid sudden output voltage changes,
which could cause logic disruptions on their loads. Preset operating points for SW1 and SW2 can be set up for:
? Normal operation: output value selected by SPI bits SWx[4:0]. Voltage transitions initiated by SPI writes to SWx[4:0] are
governed by the same DVS stepping rate that is programmed for DVSx pin initiated transitions.
? DVS: output can be higher or lower than normal operation for tailoring to application requirements. Configured by SPI bits
SWxDVS[4:0] and controlled by a DVSx pin transition.
? Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention
voltage of a given process. Set by SPI bits SWxSTBY[4:0] and controlled by a Standby event (STANDBY logically anded with
STANDBYSEC). Voltage transitions initiated by Standby are governed by the same DVS stepping that is programmed for
DVSx pin initiated transitions.
The following tables summarize the set point control and DVS time stepping applied to SW1 and SW2.
MC13892
Analog Integrated Circuit Device Data
78
Freescale Semiconductor
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