参数资料
型号: MC68MH360VR33LR2
厂商: Freescale Semiconductor
文件页数: 18/158页
文件大小: 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
标准包装: 180
系列: M683xx
处理器类型: M683xx 32-位
速度: 33MHz
电压: 5V
安装类型: 表面贴装
封装/外壳: 357-BBGA
供应商设备封装: 357-PBGA(25x25)
包装: 带卷 (TR)
QMC Supplement
Example #1
A device is operating at 25 MHz. SCC1 runs 1x10-Mbps Ethernet in half duplex, SCC2
runs 1 x 2-Mbps HDLC, SCC3 runs 1 x 64-Kbps HDLC, SCC4 runs 1 x 9.6-Kbps UART
and SMC1 runs 1 x 38-Kbps SMC UART. The following equation applies:
This yields a percentage CPM utilization of 96% meaning the device can handle these
protocols at this frequency. Note the 9.6-Kbps UART link only requires 0.4% of the CPM
bandwidth, implying that in any conguration where there is free bandwidth that it will be
possible to run a low-rate UART link.
Example #2
A device operating at 25 MHz is required to run 24 channels at 64 Kbps in QMC mode with
an additional 2 HDLC channels operating at 128 Kbps each. The following equation
applies:
Example #3
The last example shows an application with 32 QMC channels and one additional 2-Mbps
HDLC channel. The following equation applies:
Since the result above is greater than 1, this conguration may not work at 25 MHz. If a 33-
MHz operation is used, CPM utilization will drop below 1, allowing the combination to be
supported. The following equation applies:
In general, a channel combination will work if the combined load is less than 1. The
equations are scalable to frequency with the exception of the nonlinear Ethernet protocol.
Taking Ethernet into account is difcult. Designers will need to benchmark performance
for results near 1.
10
22
------
2
8
---
0.064
2.4
-------------
0.0096
2.4
----------------
0.038
0.22
-------------
+
0.96
( <1)
=
2
0.128
×
8
----------------------
24
0.064
×
2.1
-------------------------
+
0.76
( <1)
=
2
8
---
32
0.064
×
2.1
-------------------------
+
1.22
(will not work)
=
1.22
25
33
------
×
0.92
(<1)
=
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For More Information On This Product,
Go to: www.freescale.com
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