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型号： MC68MH360VR33LR2
厂商： Freescale Semiconductor
文件页数： 58/158页
文件大小： 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
标准包装： 180
系列： M683xx
处理器类型： M683xx 32-位
速度： 33MHz
电压： 5V
安装类型： 表面贴装
封装/外壳： 357-BBGA
供应商设备封装： 357-PBGA（25x25）
包装： 带卷 (TR)
QMC Supplement
C.3.2.1 Activation Procedure
During the initialization, the FREQREF signal of each U interface is enabled.
A multiplexer commanded by the QUICC32 is used to select the U interface clock master.
When the rst MC145572 is activated, its FREQREF signal synchronizes to the network.
The MC145572 then sends an interrupt to the QUICC32 (IRQ1— register NR3[1]—
meaning uao = 1 has been received) indicating that the activation process has begun. Before
responding to LT with act = 1 (which will enable the data transfer), the QUICC32 can
select, through the multiplexer, this particular FREQREF signal to be the clock master.
Since the QUICC32 has the initiative to enable the data transfer, there is no timing
constraint to react to the interrupt.
C.3.2.2 Deactivation Procedure
According to the ANSI specication T1.601-1988, prior to deactivating, the LT should
notify the NT of the pending deactivation by clearing the M4 channel dea bit towards the
NT for at least three superframes. Then, the NT can be deactivated by sending a
deactivation request.
The MC145572 not only has the ability to generate an interrupt after the reception of the
third dea bit = 0, but also after the reception of the second dea bit = 0.
When the clock-master U interface is deactivated, the QUICC32 receives an interrupt
indicating that the second dea bit = 0 has been received. The QUICC32 has then the ability
to select another activated U interface (if there is one), to be the clock master. The
QUICC32 has 12 ms (1 superframe) until receiving the next dea bit = 0, indicating the
pending deactivation, and therefore 12 ms to react to the interrupt.
If none of the U interfaces are activated, no change in the multiplex selection is required.
C.3.3 System Conguration
The following sections provide a checklist of the main features that need to be congured
for each device.
C.3.3.1 S/T-Interface Conguration
Do the following for an S/T-interface conguration:
IDL2 with time slot assigner (TSA enabled in reg. OR6[5–7]; TSA selection in
OR0 to OR5)
Slave mode (DCL & FSC are input) - (pin M/S to GND)
TCLK enabled at 2.048 MHz (OR7[5] = 1; BR13[5] = 0;
BR7[2] = 1)
D channel contention procedure disabled (BR7[6] = 1)
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For More Information On This Product,
Go to: www.freescale.com
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