参数资料
型号: MCIMX534AVV8C
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封装: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件页数: 104/178页
文件大小: 4711K
代理商: MCIMX534AVV8C
Electrical Characteristics
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3
Freescale Semiconductor
31
4.3.2.3
DDR3 Mode I/O DC Parameters
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The
parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Differential Input Logic High
Vih(diff)
0.26
See Note2
Differential Input Logic Low
Vil(diff)
See Note2
-0.26
Input current (no pull-up/down)
Iin
Vin = 0 V
Vin=OVDD
1
μA
Pull-up/Pull-down impedance Mismatch
-15
+15
%
240 Ohm unit calibration resolution
10
Ohm
Keeper Circuit Resistance
1403
—k
Ω
1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
3 Use an off-chip pull resistor of less than 60 k
Ω to override this keeper.
Table 13. DDR3 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
0.8*OVDD1
1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3)
——
V
Low-level output voltage
Vol
0.2*OVDD
V
DC input Logic High
VIH(dc)
Vref2+0.1
2 Vref – DDR3 external reference voltage
—OVDD
V
DC input Logic Low
VIL(dc)
OVSS
Vref-0.1
V
Differential input Logic High
VIH(diff)
0.2
See Note3
V
Differential input Logic Low
VIL(diff)
See Note3
—-0.2
V
Over/undershoot peak
Vpeak
0.4
V
Over/undershoot area
(above OVDD or below OVSS)
Varea
0.67
V x
nS
Termination Voltage
Vtt
Vtt tracking OVDD/2
0.49*OVDD
Vref
0.51*OVDD
V
Input current (no pull-up/down)
Iin
VI = 0 V
VI=OVDD
1
μA
Pull-up/Pull-down impedance mismatch
Minimum impedance
configuration
——
3
Ω
240
Ω unit calibration resolution
10
Ω
Keeper Circuit Resistance
1304
—k
Ω
Table 12. LPDDR2 I/O DC Electrical Parameters1 (continued)
相关PDF资料
PDF描述
MCP23008T-E/SO 8 I/O, PIA-GENERAL PURPOSE, PDSO18
MCP23008-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/SS 8 I/O, PIA-GENERAL PURPOSE, PDSO20
MCP23008-E/P 8 I/O, PIA-GENERAL PURPOSE, PDIP18
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