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参数资料
型号： MCIMX534AVV8C
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封装： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件页数： 171/178页
文件大小： 4711K
代理商： MCIMX534AVV8C
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3
92
Freescale Semiconductor
Electrical Characteristics
Table 60 shows timing characteristics of signals presented in Figure 48 and Figure 49.
Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level)
ID
Parameter
Symbol
Value
Description
Unit
IP5
Display interface clock period
Tdicp
(1)
Display interface clock. IPP_DISP_CLK
ns
IP6
Display pixel clock period
Tdpcp
DISP_CLK_PER_PIXEL
× Tdicp
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
ns
IP7
Screen width time
Tsw
(SCREEN_WIDTH)
× Tdicp
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter2.
ns
IP8
HSYNC width time
Thsw
(HSYNC_WIDTH)
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
ns
IP9
Horizontal blank interval 1
Thbi1
BGXP
× Tdicp
BGXP—width of a horizontal blanking
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
ns
IP10
Horizontal blank interval 2
Thbi2
(SCREEN_WIDTH –
BGXP – FW)
× Tdicp
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
ns
IP12
Screen height
Tsh
(SCREEN_HEIGHT)
× Tsw
SCREEN_HEIGHT— screen height in lines
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
ns
IP13
VSYNC width
Tvsw
VSYNC_WIDTH
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP
× Tsw
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
ns
IP15
Vertical blank interval 2
Tvbi2
(SCREEN_HEIGHT –
BGYP – FH)
× Tsw
Width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
ns
相关PDF资料
PDF描述
MCP23008T-E/SO 8 I/O, PIA-GENERAL PURPOSE, PDSO18
MCP23008-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/SS 8 I/O, PIA-GENERAL PURPOSE, PDSO20
MCP23008-E/P 8 I/O, PIA-GENERAL PURPOSE, PDIP18
相关代理商/技术参数
参数描述
MCIMX534AVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX534AVV8CR2 功能描述:处理器 - 专门应用 iMX53 Rev 2.1 Auto RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX535DVV1B 功能描述:处理器 - 专门应用 IMX53 REV 2.0 COMM RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX535DVV1C 功能描述:处理器 - 专门应用 IMX53 REV 2.1 COMM RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX535DVV1C 制造商:Freescale Semiconductor 功能描述:IMX53 REV 2.1 COMM
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