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参数资料
型号： MCIMX534AVV8C
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封装： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件页数： 97/178页
文件大小： 4711K
代理商： MCIMX534AVV8C
Electrical Characteristics
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3
Freescale Semiconductor
25
Irreversible damage to the i.MX53xA processor (worst-case scenario)
4.2.1
Power-Up Sequence
The following observations should be considered:
The consequent steps in power up sequence should not start before the previous step supplies have
been stabilized within 90-110% of their nominal voltage, unless stated otherwise.
NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time
clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.
The VCC should be powered ON together, or any time after NVCC_SRTC_POW.
NVCC_CKIH should be powered ON after VCC is stable and before other IO supplies
(NVCC_xxx) are powered ON.
IO Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede
NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is
stabilized. Within this group, the supplies can be powered-up in any order.
IO Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after
NVCC_CKIH is stable.
In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator
(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their
internal regulators power source.
If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage
during the power-up, it is recommended to activate the VDD_REG before or at the same time
with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that
the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 k
Ω when it is inactive.
VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered
on after VCC and before NVCC_EMI_DRAM. The sequence should be:
VCC
→VDD_REG →NVCC_EMI_DRAM
VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other power
signal.
VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.
VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come
before POR.
TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This
is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is
powered ON before the other.
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail reaches its working voltage.
相关PDF资料
PDF描述
MCP23008T-E/SO 8 I/O, PIA-GENERAL PURPOSE, PDSO18
MCP23008-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/SS 8 I/O, PIA-GENERAL PURPOSE, PDSO20
MCP23008-E/P 8 I/O, PIA-GENERAL PURPOSE, PDIP18
相关代理商/技术参数
参数描述
MCIMX534AVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX534AVV8CR2 功能描述:处理器 - 专门应用 iMX53 Rev 2.1 Auto RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX535DVV1B 功能描述:处理器 - 专门应用 IMX53 REV 2.0 COMM RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX535DVV1C 功能描述:处理器 - 专门应用 IMX53 REV 2.1 COMM RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX535DVV1C 制造商:Freescale Semiconductor 功能描述:IMX53 REV 2.1 COMM
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