Modules List
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3
Freescale Semiconductor
15
SRTC
Secure Real
Time Clock
Security
The SRTC incorporates a special system state retention register (SSRR)
that stores system parameters during system shutdown modes. This
register and all SRTC counters are powered by dedicated supply rail
NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized
separately even if all other supply rails are shut down. The power for this
block comes from NVCC_SRTC_POW supply. When this supply is driven
by the MC13892 power management controller, this block can be power
backed up through the coin-cell feature of the MC13892. This register is
helpful for storing warm boot parameters. The SSRR also stores the system
security state. In case of a security violation, the SSRR mark the event
(security violation indication).
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface used on the i.MX53A
processor to provide connectivity with off-chip audio peripherals. The SSI
interfaces connect internally to the AUDMUX for mapping to external ports.
The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,
and AC-97), bit depths (up to 24 bits per word), and clock/frame sync
options.
Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an
external DMA controller in order to minimize its impact on system
performance. The second pair of FIFOs provides hardware interleaving of
a second audio stream, which reduces CPU overhead in use cases where
two time slots are being used simultaneously.
IPTP
IEEE1588
Precision Time
Protocol
Connectivity
Peripherals
The IEEE 1588-2002 (version 1) standard defines a precision time protocol
(PTP) - which is a time-transfer protocol that enables synchronization of
networks (for example, Ethernet), to a high degree of accuracy and
precision.
The IEEE1588 hardware assist is composed of the two blocks: time stamp
unit and real time clock, which provide the timestamping protocol’s
functionality, generating and reading the needed timestamps.
The hardware-assisted implementation delivers more precise clock
synchronization at significantly lower CPU load compared to purely
software implementations.
Temperature
Monitor
(Part of SATA
Block)
System
Control
Peripherals
The temperature sensor is an internal module to the i.MX53xA that monitors
the die temperature. The monitor is capable in generating SW interrupt, or
trigger the CCM, to reduce the core operating frequency.
TVE
TV Encoder
Multimedia
The TV encoder, version 2.1 is implemented in conjunction with the image
processing unit (IPU) allowing handheld devices to display captured still
images and video directly on a TV or LCD projector. It supports composite
PAL/NTSC, VGA, S-video, and component up to HD1080p analog video
outputs.
TZIC
TrustZone Aware
Interrupt
Controller
ARM/Control
The TrustZone interrupt controller (TZIC) collects interrupt requests from all
i.MX53xA sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description