参数资料
型号: MCIMX534AVV8C
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封装: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件页数: 160/178页
文件大小: 4711K
代理商: MCIMX534AVV8C
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3
82
Freescale Semiconductor
Electrical Characteristics
4.7.7
I2C Module Timing Parameters
This section describes the timing parameters of the I2C module. Figure 43 depicts the timing of I2C
module, and Table 56 lists the I2C module timing characteristics.
Figure 43. I2C Bus Timing
Table 56. I2C Module Timing Parameters
ID
Parameter
Standard Mode
Supply Voltage =
1.65 V–1.95 V, 2.7 V–3.3 V
Fast Mode
Supply Voltage =
2.7 V–3.3 V
Unit
Min
Max
Min
Max
IC1
I2CLK cycle time
10
2.5
s
IC2
Hold time (repeated) START condition
4.0
0.6
s
IC3
Set-up time for STOP condition
4.0
0.6
s
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
3.452
2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
0.92
s
IC5
HIGH Period of I2CLK Clock
4.0
0.6
s
IC6
LOW Period of the I2CLK Clock
4.7
1.3
s
IC7
Set-up time for a repeated START condition
4.7
0.6
s
IC8
Data set-up time
250
1003
3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
—ns
IC9
Bus free time between a STOP and START condition
4.7
1.3
s
IC10
Rise time of both I2DAT and I2CLK signals
1000
20 + 0.1Cb
4
4 C
b = total capacitance of one bus line in pF.
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
300
20 + 0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
400
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2DAT
I2CLK
IC1
相关PDF资料
PDF描述
MCP23008T-E/SO 8 I/O, PIA-GENERAL PURPOSE, PDSO18
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MCP23S08T-E/ML 8 I/O, PIA-GENERAL PURPOSE, PQCC20
MCP23S08T-E/SS 8 I/O, PIA-GENERAL PURPOSE, PDSO20
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