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参数资料
| 型号： | ML60852A |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 13/82页 |
| 文件大小： | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
19/81
(2) EP0 Receive packet ready interrupt
This is used mainly during the reception of a data packet in a control write transfer.
Operation
Source of operation
Description (conditions, responses, etc.)
EP0 Receive packet ready
interrupt generation
ML60852A
The EP0 receive packet ready bit (D0 of EP0STAT) is
asserted during a control write transfer when the
processing has changed from the setup stage to the data
stage, and the ML60852A has detected EOP of the data
packet and has stored the data without error in the EP0
receive FIFO. The end of a packet is recognized when an
EOP has arrived in the cases of both full packets and short
packets.
An interrupt is generated at this time, if the EP0 receive
packet ready interrupt enable bit (D6 of INTENBL1) has
been asserted.
(EOP: End of packet)
End of EP0 receive
packet ready interrupt
Local MCU (firmware)
In the case of EP0 reception, after the number of bytes of
the EP0 receive FIFO data indicated by the EP0 receive
byte count register (EP0RXCNT) has been read, write a “1”
to the EP0 receive packet ready bit (bit D0 of EP0STAT).
(This status is reset when a “1” is written in this bit.)
Note:
A short packet is a packet with a number of bytes less than the maximum packet size.
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相关代理商/技术参数 |
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| ML60852ATBZ010 | 功能描述:USB 接口集成电路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 产品:USB 2.0 数据速率: 接口类型:SPI 工作电源电压:3.15 V to 3.45 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全称:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全称:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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