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参数资料
| 型号： | ML60852A |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 9/82页 |
| 文件大小： | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
16/81
(6) Data packet transmission and reception procedure during isochronous transfer mode
Transfer of data is the major function in the isochronous transfermode. When carrying out isochronous transfer
between the ML60852A and the host, the following packet communications are carried out via the USB bus for the
data transfer of each packet.
(a) Token packet transfer (IN token or OUT token) from the host to the ML60852A.
(b) Data packet transfer in the desired direction (from the host to the device or from the device to the host).
In the isochronous transfer mode, there is no handshaking that reports whether or not the packet transfer was
done normally.
The ML60852A requests the local MCU to send or receive packet data by asserting the
INTR pin. The
interrupt cause is SOF. Upon receiving this interrupt, the local MCU writes the packet data into the transmit
FIFO of the EP set for transmission (ISO IN) in the isochronous transfer mode, or reads out data from the
receive FIFO of the EP set for reception (ISO OUT) in the isochronous transfer mode.
The above procedures of transferring one packet of data are explained below for transmission and reception
separately.
1)
During transmission
The EP for ISO IN has a two-layer FIFO configuration. One FIFO is used for storing the packet data that is
written in by the MCU via the local bus. The other FIFO is used for transmitting the stored data to the USB bus
when an IN token is received. The roles of the two FIFOs are interchanged when an SOF packet is received.
Upon receiving an SOF interrupt, the local MCU writes the data to be transmitted during the next frame into the
corresponding transmit FIFO of the EP of the ML60852A. When the host transmits an IN token packet, the
ML60852A transmits to the host the packet data written in the transmit FIFO during the previous frame.
2)
During reception
The EP for ISO OUT has a two-layer FIFO configuration. One FIFO is used for storing the packet data that is
output to the local bus when the MCU reads the received packet data. The other FIFO is used for storing the
packet data received from the USB bus. The roles of the two FIFOs are interchanged when an SOF packet is
received.
Upon receiving an SOF interrupt, the local MCU reads out the data that has been received during the previous
frame from the corresponding receive FIFO of the EP of the ML60852A. When the host transmits an OUT
token and a data packet to the ML60852A, the ML60852A stores that received data packet in the receive FIFO,
and that data packet is read out by the local MCU during the next frame.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成电路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 产品:USB 2.0 数据速率: 接口类型:SPI 工作电源电压:3.15 V to 3.45 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全称:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全称:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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