参数资料
型号: ML60852A
厂商: LAPIS SEMICONDUCTOR CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: PLASTIC, QFP-44
文件页数: 54/82页
文件大小: 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
57/81
EP0 Receive Byte Counter Register (EP0RXCNT)
Address
0 x 58
Type
6-Bit data
Access type
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Receive byte count (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is
done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case
of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value
and reads out the data of one packet from the EP0 Receive FIFO.
The EP0RXCNT register is cleared under the following conditions.
1. When the local MCU resets the EP receive packet ready bit.
2. When a setup packet is received.
3. When the local MCU writes a “0” into the stall bit.
EP1, 2 Receive Byte Counter Registers (EP1, 2RXCNT)
Address
0 x 59, 5A
Type
7-Bit data
Access type
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Receive byte count (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is
done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case
of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value
and reads out the data of one packet from the EP1/2 Receive FIFO.
This register will be invalid when the transfer direction of the EP is set for transmission.
The EP1,2RXCNT register is cleared under the following conditions.
1. When an OUT token is received for the EP.
2. When the local MCU resets the EP receive packet ready bit.
3. When the local MCU writes a “0” into the stall bit.
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