参数资料
型号: ML60852A
厂商: LAPIS SEMICONDUCTOR CO LTD
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封装: PLASTIC, QFP-44
文件页数: 28/82页
文件大小: 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
33/81
FUNCTIONS OF REGISTERS
EP0 Transmit FIFO (EP0TXFIFO)
Address
0 x 70
Type
Byte data
Access type
Write only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
xxxx
xx
After a bus reset
x
xxxx
xx
Definition
EP0 Transmit data
The EP0 transmit data can be written in by writing to the address 70h.
The transmit data to the host in the data stage during a control read transfer is stored in EP0TXFIFO. When the
ML60852A issues an EP0 transmit packet ready interrupt request, the local MCU writes the transmit data to the
address 70h.
It is possible to write the packet data successively by writing continuously.
The EP0TXFIFO is cleared under the following conditions.
1. When an ACK signal is received from the host for the data transmission from EP0
2. When a setup packet is received
EP0 Receive FIFO (EP0RXFIFO)
Address
0 x 78
Type
Byte data
Access type
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
xxxx
xx
After a bus reset
x
xxxx
xx
Definition
EP0 Receive data
The receive data from the host computer in the data sate during a control Write transfer is stored in EP0RXFIFO.
EP0 receive data can be read out by the local MCU through reading the address 78h when the ML60852A issues an
EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by reading
continuously.
The EP0RXFIFO is cleared under the following conditions:
1. When the local MCU resets EP0 receive packet ready bit.
2. When a setup packet is received.
3. When the local MCU writes a “0” in the stall bit.
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