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参数资料
| 型号： | ML60852A |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 15/82页 |
| 文件大小： | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
21/81
(4) Receive packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk)
These interrupts are generated when the respective EP has received an appropriate data packet from the USB
bus and the local MCU can read that data.
Operation
Source of operation
Description (conditions, responses, etc.)
Receive packet ready
interrupt generation
ML60852A
The receive packet ready bit (D0) of the corresponding EP
status register (EPnSTAT) is asserted during data
reception when the EOP of the data packet has been
received and the data has been stored without error in the
corresponding FIFO. The end of a packet is recognized
when an EOP has arrived in the cases of both full packets
and short packets.
An interrupt is generated at this time, if the corresponding
receive packet ready interrupt enable bit has been
asserted.
(EOP: End of packet)
End of receive packet ready
interrupt
Local MCU (firmware)
After the number of bytes in the receive FIFO data
(EPnFIFO) indicated by the corresponding receive byte
count register (EPnRXCNT) has been read, write a “1” into
the receive packet ready bit D0 of the corresponding EP
status register (EPnSTAT). (This status is reset when a “1”
is written in this bit.)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成电路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 产品:USB 2.0 数据速率: 接口类型:SPI 工作电源电压:3.15 V to 3.45 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全称:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全称:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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