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参数资料
型号： MT28F320A18
厂商： Micron Technology, Inc.
英文描述： FLASH MEMORY
中文描述： 闪存
文件页数： 25/37页
文件大小： 558K
代理商： MT28F320A18
2 MEG x 16
1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
PRELIMINARY
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory
MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
2002, Micron Technology Inc.
25
CHIP PROTECTION REGISTER
A 128-bit protection register can be used to fulfill
the security considerations in the system (preventing
the device substitution).
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit unchangeable
number. The other segment is left blank for customers
to program as desired. (See Figure 8).
Figure 8:
Protection Register Memory Map
Reading the Chip Protection Register
The chip protection register is read in the device
identification mode, loading the 90h command to the
bank containing address 00h. Once in this mode,
READ cycles from addresses shown in Table 10 retrieve
the specified information. To return to the read array
mode, write the READ ARRAY command (FFh).
Programming the Chip Protection
Register
Executing the PROTECTION PROGRAM command
enables the customer to program the user portion of
the protection register. First, write the PROTECTION
PROGRAM SETUP command, C0h; then write address
and data to program.
Attempts should not be made to address PROTEC-
TION PROGRAM commands outside the defined pro-
tection register address space. Attempting to program
to a previously locked protection register segment will
result in a status register error (program error bit SR4
and lock error bit SR1 = 1)
Locking the Chip Protection Register
The customer-programmable segment of the pro-
tection register can be locked by programming bit 1 of
the PR lock location to "0". Bit 0 of this location is pro-
grammed to a “0” at the Micron factory to protect the
unique device number. Bit 1 is set using the PROTEC-
TION PROGRAM command to program FFFDh to the
PR lock location. After these bits have been pro-
grammed, no further changes can be made to the val-
ues stored in the protection register. PROTECTION
PROGRAM commands to a locked section will result in
a status register error program error bit SR4 and lock
error bit SR1 will be set to 1. Protection register lockout
is not reversible.
V
PP
/V
CC
Program and Erase Voltages
The MT28F320A18 Flash memory provides in-sys-
tem programming and erase with V
PP
in the 0.9V–
1.95V (V
PP1
) range. The 12V V
PP
(V
PP2
) mode program-
ming is offered for compatibility with existing pro-
gramming
equipment.
algorithm is enabled at V
PP
= V
PP2
.
The device can withstand 100,000 WRITE/ERASE
operations when V
PP
= V
PP1
or 100 WRITE/ERASE
operations and 10 cumulative hours when V
PP
= V
PP2
.
In addition to the flexible block locking, the V
PP
pro-
gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V
PP
is below V
PPLK
, any PROGRAM or ERASE
operation will result in an error, prompting the corre-
sponding status register bit (SR3) to be set.
During WRITE and ERASE operations, the WSM
monitors the V
PP
voltage level. WRITE/ERASE opera-
tions are allowed only when V
PP
is within the range
specified in T
ABLE
11.
When V
CC
is below V
LKO
or below V
PPLK
, any
WRITE/ERASE operation will be disabled.
The
fast
programming
4 Words
Factory-Programmed
4 Words
User-Programmed
PR Lock
0
88h
85h
84h
81h
80h
Table 11:
V
PP
Range (V)
MIN
0.9
11.4
MAX
1.95
12.6
In-System (V
PP
1)
In-Factory (V
PP
2)
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