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参数资料
| 型号： | MT48H8M16LFB4-75 IT:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 15/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1530-6 |
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128Mb: x16 Mobile SDRAM
Commands
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11, BA0, BA1. See “Mode Register Defini-
tion” on page 8. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER
commands can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until t MRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a precharge command is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQ subject to the logic
level on the DQM inputs 2 clocks earlier. If a given DQM signal was registered HIGH, the
corresponding DQ will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQ will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be
ignored, and a write will not be executed to that byte/column location.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数 |
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| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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