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参数资料
| 型号： | MT48H8M16LFB4-75 IT:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 21/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1530-6 |
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128Mb: x16 Mobile SDRAM
Operation
Figure 11:
Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
BANK,
COL n
READ
BANK,
COL a
READ
BANK,
COL x
D OUT
n
READ
BANK,
COL m
D OUT
a
NOP
D OUT
x
NOP
D OUT
m
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
D OUT
n
D OUT
a
D OUT
x
D OUT
m
CL = 3
TRANSITIONING DATA
DON’T CARE
Notes:
1. Each READ command may be to any bank. DQM is LOW.
The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13 on
page 22. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE
command (DQM latency is 2 clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQ will go High-Z (or remain High-
Z), regardless of the state of the DQM signal, provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 14
on page 23, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is
needed. A fixed-length READ burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated). The PRECHARGE command should be issued x cycles before the clock edge at
which the last desired data element is valid, where x = CL - 1. This is shown in Figure 14
for each possible CL; data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until t RP is met. Note that part of the row
precharge time is hidden during the access of the last data element(s).
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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