- 您现在的位置：买卖IC网 > Datasheet目录345 > MT48H8M16LFB4-75 IT:K TR (Micron Technology Inc)IC SDRAM 128MBIT 133MHZ 54VFBGA Datasheet资料下载
参数资料
| 型号： | MT48H8M16LFB4-75 IT:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 25/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1530-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页
128Mb: x16 Mobile SDRAM
Operation
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to
a different bank.
Figure 17:
WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DQ
D IN
n
D IN
n +1
TRANSITIONING DATA
DON’T CARE
Notes:
1. BL = 2. DQM is LOW.
Figure 18:
WRITE-to-WRITE
C LK
T0
T1
T2
C OMMAND
ADDRE SS
DQ
WRITE
BANK,
C OL n
D IN
n
NOP
D IN
n +1
WRITE
BANK,
C OL b
D IN
b
DON ’ T C ARE
WR of at least one clock plus time, regardless of frequency.
Notes:
1. DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 20 on page 26. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated). The PRECHARGE command should be issued t WR after the clock edge at which
the last desired input data element is registered. The auto precharge mode requires a
t
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure 21 on page 27. Data n + 1 is
either the last of a burst of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until t RP is met.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| MTC100-JA2-P34 | CONTACT INSERT PIN |
| MX841BE | IC CONVERTER WHITE LED 8-SOIC |
| MXHV9910BTR | IC LED DRIVER HIGH BRIGHT 8-SOIC |
| MXN12FB12F | MOTOR BRUSHED DC 12V 2922RPM |
| MXN13FB08B1 | MOTOR BRUSHED DC 8V 4714RPM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
发布紧急采购，3分钟左右您将得到回复。