- 您现在的位置：买卖IC网 > PDF目录225025 > RC28F256P33T85A (NUMONYX) 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 PDF资料下载
参数资料
| 型号： | RC28F256P33T85A |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封装： | BGA-64 |
| 文件页数： | 14/96页 |
| 文件大小： | 1378K |
| 代理商： | RC28F256P33T85A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
November 2007
Datasheet
Order Number: 314749-05
21
Numonyx StrataFlash Embedded Memory (P33)
Table 7:
QUAD+ SCSP Signal Descriptions
Symbol
Type
Name and Function
A[MAX:0]
Input
ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit:
A[23:0]; 512-Mbit: A[24:0]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the
dual-die 512-Mbit configuration is accomplished by setting A24 high (VIH).
DQ[15:0]
Input/
Output
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
ADV#
Input
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
F1-CE#
Input
FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state. Note: F2-CE# is a NC for this part
WARNING: All chip enables must be high when device is not in use.
CLK
Input
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During
synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid
CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
F1-OE#
Input
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z. Note: F2-OE# is a NC for this part.
RST#
Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT
Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR 10, WT) determines its polarity when asserted. WAIT’s active output is VOL or
VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
In asynchronous page mode, and all write modes, WAIT is deasserted.
WE#
Input
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WP#
Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
VPP
Power/
lnput
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VCC
Power
Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
Power
Output Power Supply: Output-driver source voltage.
VSS
Power
Ground: Connect to system ground. Do not float any VSS connection.
RFU
—
Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement.
These should be treated in the same way as a Don’t Use (DU) signal.
DU
—
Don’t Use: Do not connect to any other signal, or power supply; must be left floating.
NC
—
No Connect: No internal connection; can be driven or floated.
相关PDF资料 |
PDF描述 |
|---|---|
| RC28F160C3TC90 | 1M X 16 FLASH 3V PROM, 90 ns, PBGA64 |
| RC28F160C3BD70 | 1M X 16 FLASH 3V PROM, 70 ns, PBGA64 |
| RC4194K | DUAL OUTPUT, ADJUSTABLE MIXED REGULATOR, MBFM9 |
| RM4194K | DUAL OUTPUT, ADJUSTABLE MIXED REGULATOR, MBFM9 |
| RC4194D | DUAL OUTPUT, ADJUSTABLE MIXED REGULATOR, CDIP14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RC28F256P33T85B | 制造商:Micron Technology Inc 功能描述:256MB, KEARNY EBGA 3.0 - Tape and Reel |
| RC28F256P33TFA | 功能描述:IC FLASH 256MBIT 95NS 64EZBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:Axcell™ 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ |
| RC28F256P33TFE | 功能描述:IC FLASH 256MBIT 64EZBGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:Axcell™ 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| RC28F320C3 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| RC28F320C3BA100 | 功能描述:IC FLASH 32MBIT 100NS 64BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
发布紧急采购，3分钟左右您将得到回复。