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参数资料
| 型号： | RC28F256P33T85A |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封装： | BGA-64 |
| 文件页数： | 52/96页 |
| 文件大小： | 1378K |
| 代理商： | RC28F256P33T85A |
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Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
56
Order Number: 314749-05
To perform an asynchronous page-mode read, an address is driven onto the address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been
deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven
high to latch the address, or it must be held low throughout the read cycle. CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated
and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial
In asynchronous page mode, four data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest two address bits determine which word of the
4-word page is output from the data buffer at any given time.
11.2.2
Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see Section
11.1.0.3, “Latency Count” on page 50). Subsequent data is output on valid CLK edges
following a minimum delay. However, for a synchronous non-array read, the same word
of data will be output on successive clock edges until the burst length requirements are
satisfied. Refer to the following waveforms for more detailed information:
11.2.3
Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device identifier code, block-lock status, protection register data, or configuration
register data (see Section 9.6, “Device Command Bus Cycles” on page 44 for details on
issuing the Read Device Identifier command). Table 30, “Device Identifier Information”
on page 56 and Table 31, “Device ID codes” on page 57 show the address offsets and
data values for this device.
Table 30: Device Identifier Information (Sheet 1 of 2)
Item
Address(1)
Data
Manufacturer Code
0x00
0089h
Device ID Code
0x01
ID (see
Block Lock Configuration:
BBA + 0x02
Lock Bit:
Block Is Unlocked
DQ0 = 0b0
Block Is Locked
DQ0 = 0b1
Block Is not Locked-Down
DQ1 = 0b0
Block Is Locked-Down
DQ1 = 0b1
Read Configuration Register
0x05
RCR Contents
Lock Register 0
0x80
PR-LK0
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