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参数资料
| 型号： | RC28F256P33T85A |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封装： | BGA-64 |
| 文件页数： | 44/96页 |
| 文件大小： | 1378K |
| 代理商： | RC28F256P33T85A |
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November 2007
Datasheet
Order Number: 314749-05
49
Numonyx StrataFlash Embedded Memory (P33)
Note:
Always clear the Status Register prior to resuming erase operations. It avoids Status
Register ambiguity when issuing commands during Erase Suspend. If a command
sequence error occurs during an erase-suspend state, the Status Register contains the
command sequence error status (SR[7,5,4] set). When the erase operation resumes
and finishes, possible errors during the erase operation cannot be detected via the
Status Register because it contains the previous error status.
11.1.0.1
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.Read Configuration
Register
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 9.6, “Device Command
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 11.2.3, “Read Device Identifier” on page 56).
The RCR is shown in Table 26. The following sections describe each RCR bit.
2
Program Suspend Status (PSS)
0 = Program suspend not in effect.
1 = Program suspend in effect.
1Block-Locked Status (BLS)
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0BEFP Write Status (BWS)
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
Table 25: Status Register Description (Sheet 2 of 2)
Status Register (SR)
Default Value = 0x80
Table 26: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode
RES
Latency Count
WAIT
Polarity
Data
Hold
WAIT
Delay
Burst
Seq
CLK
Edge
RES
Burst
Wrap
Burst Length
RM
R
LC[2:0]
WP
DH
WD
BS
CE
R
BW
BL[2:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
15
Read Mode (RM)
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
14
Reserved (R)
Reserved bits should be cleared (0)
13:11
Latency Count (LC[2:0])
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
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