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参数资料
| 型号： | RK80532RC056128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2400 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, PGA2-478 |
| 文件页数： | 18/99页 |
| 文件大小： | 4142K |
| 代理商： | RK80532RC056128 |
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Datasheet
25
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. VHavg is the statistical average of the VH measured by the oscilloscope.
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. VHavg can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
10.
V
CROSS is defined as the total variation of all crossing voltages as defined in note 2.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in this chapter.
5. Refer to processor I/O Buffer Models for I/V characteristics.
6. The VCC referred to in these specifications is the instantaneous VCC.
7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50
as indicated in Figure 6.
8. Leakage to VSS with pin held at VCC.
9. Leakage to VCC with Pin held at 300 mV.
Table 9.
System Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Fig
Notes1
VL
Input Low Voltage
–0.150
0.000
N/A
V
VH
Input High Voltage
0.660
0.710
0.850
V
VCROSS(abs)
Absolute Crossing
Point
0.250
N/A
0.550
V
2, 3, 8
VCROSS(rel)
Relative Crossing
Point
0.250 +
0.5(VHavg–0.710)
N/A
0.550 +
0.5(VHavg–0.710)
V
2, 3, 8, 9
V
CROSS
Range of Crossing
Points
N/A
0.140
V
2, 10
VOV
Overshoot
N/A
VH + 0.3
V
4
VUS
Undershoot
–0.300
N/A
V
5
VRBM
Ringback Margin
0.200
N/A
V
6
V
TM
Threshold Margin
VCROSS – 0.100
N/A
VCROSS + 0.100
V
7
Table 10. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
GTLREF
Reference Voltage
2/3 VCC – 2%
2/3 VCC + 2%
V
VIH
Input High Voltage
1.10*GTLREF
VCC
V
2, 6
VIL
Input Low Voltage
0.0
0.9*GTLREF
V
3, 4, 6
VOH
Output High Voltage
N/A
VCC
V
7
IOL
Output Low Current
N/A
50
mA
6
IHI
Pin Leakage High
N/A
100
A
8
ILO
Pin Leakage Low
N/A
500
A
9
RON
Buffer On Resistance
7
11
5
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相关代理商/技术参数 |
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