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参数资料
| 型号： | RK80532RC056128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2400 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, PGA2-478 |
| 文件页数： | 25/99页 |
| 文件大小： | 4142K |
| 代理商： | RK80532RC056128 |
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Datasheet
31
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge
at 0.5 * VCC.
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion and before the deassertion of PROCHOT# for the processor to complete current instruction
execution.
6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP
signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of
0.5 V/ns.
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
Table 19. Miscellaneous Signals AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes1, 2, 3, 6
T35: Asynch GTL+ Input Pulse Width
2
BCLKs
T36: PWRGOOD to RESET# deassertion time
1
10
ms
T37: PWRGOOD Inactive Pulse Width
10
BCLKs
4
T38: PROCHOT# pulse width
500
s
5
T39: THERMTRIP# to VCC Removal
0.5
s
T40: FERR# Valid Delay from STPCLK# deassertion
0
5
BCLKs
Table 20. System Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Setup Time
4
BCLKs
1
T46: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Hold Time
2
20
BCLKs
2
Table 21. TAP Signals AC Specifications
Parameter
Min
Max
Unit
Figure
Notes1, 2, 3
T55: TCK Period
60.0
ns
T56: TCK Rise Time
10.0
ns
4
T57: TCK Fall Time
10.0
ns
4
T58: TMS Rise Time
8.5
ns
4
T59: TMS Fall Time
8.5
ns
4, 9
T61: TDI Setup Time
0
ns
5, 7
T62: TDI Hold Time
3
ns
5, 7
T63: TDO Clock to Output Delay
3.5
ns
6
T64: TRST# Assert Time
2
TCK
8, 9
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