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| 型号： | RK80532RC056128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2400 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, PGA2-478 |
| 文件页数： | 70/99页 |
| 文件大小： | 4142K |
| 代理商： | RK80532RC056128 |
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72
Datasheet
Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package
5.2
Alphabetical Signals Reference
Table 36. Signal Description (Sheet 1 of 8)
Name
Type
Description
A[35:3]#
Input/
Output
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
must connect the appropriate pins of all agents on the Intel Celeron processor
on 0.13 micron process. A[35:3]# are protected by parity signals AP[1:0]#.
A[35:3]# are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a subset
of the A[35:3]# pins to determine power-on configuration. See Section 7.1 for
more details.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
is supported only in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new
transaction.
ADSTB[1:0]#
Input/
Output
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as follows:
AP[1:0]#
Input/
Output
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is
high if an even number of covered signals are low, and low if an odd number of
covered signals are low. This allows parity to be high when all the covered
signals are high. AP[1:0]# should connect the appropriate pins of all Celeron
processor on 0.13 micron process system bus agents. The following table
defines the coverage model of these signals.
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the system bus frequency. All
processor system bus agents must receive these signals to drive their outputs
and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB0#
A[35:17]#
ADSTB1#
Request Signals
Subphase 1
Subphase 2
A[35:24]#
AP0#
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80532RC060128S L6ZY | 制造商:Intel 功能描述:MPU Celeron? Processor 0.13um 2.5GHz 478-Pin FCPGA2 制造商:Intel 功能描述:NORTHWOOD; MPU CELERON 0.13UM 2.5GHZ 478PIN FCPGA2 - Trays |
| RK80532RC060128SL72B | 功能描述:IC CELERON 2.5GHZ 478FC-PGA2 RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| RK80532RC064128 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RK805346RE067256 | 制造商:Intel 功能描述:TRAY CELERON D 330 - Trays |
| RK80546KF0871M | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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