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参数资料
| 型号： | RK80532RC056128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2400 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, PGA2-478 |
| 文件页数： | 19/99页 |
| 文件大小： | 4142K |
| 代理商： | RK80532RC056128 |
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26
Datasheet
Electrical Specifications
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0, “System Bus Signal Quality Specifications”.
4. The VCC referred to in these specifications refers to instantaneous VCC.
5. This specification applies to the asynchronous GTL+ signal group.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load shown in Figure 6.
7. Refer to the processor I/O Buffer Models for I/V characteristics.
8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50
as indicated in Figure 6 for the
Asynchronous GTL+ signals.
9. Leakage to VSS with pin held at VCC.
10.Leakage to VCC with pin held at 300 mV.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. The TAP signal group must comply with the signal quality specifications in Chapter 3.0, “System Bus Signal
4. Refer to I/O Buffer Models for I/V characteristics.
5. The VCC referred to in these specifications refers to instantaneous VCC.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load shown in Figure 6.
7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50
as indicated in Figure 6 for the TAP
Signals.
8. VHYS represents the amount of hysteresis, nominally centered about 1/2 VCC for all TAP inputs.
9. Leakage to VSS with pin held at VCC.
10.Leakage to VCC with pin held at 300 mV.
Table 11. Asynchronous GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VIH
Input High Voltage Asynch GTL+
1.10*GTLREF
VCC
V
3, 4, 5
VIL
Input Low Voltage Asynch. GTL+
0
0.9*GTLREF
V
5
VOH
Output High Voltage
N/A
VCC
V
2, 3, 4
IOL
Output Low Current
N/A
50
mA
6, 8
IHI
Pin Leakage High
N/A
100
A
9
ILO
Pin Leakage Low
N/A
500
A
10
Ron
Buffer On Resistance Asynch GTL+
7
11
5, 7
Table 12. PWRGOOD and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VHYS
Input Hysteresis
200
300
mV
8
VT+
Input Low to High
Threshold Voltage
1/2*(VCC + VHYS_MIN)
1/2*(VCC + VHYS_MAX)
V
5
VT-
Input High to Low
Threshold Voltage
1/2*(VCC – VHYS_MAX)
1/2*(VCC – VHYS_MIN)
V
5
VOH
Output High Voltage
N/A
VCC
V
2, 3, 5
IOL
Output Low Current
N/A
40
mA
6, 7
IHI
Pin Leakage High
N/A
100
A
9
ILO
Pin Leakage Low
N/A
500
A
10
R
ON
Buffer On Resistance
8.75
13.75
4
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