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| 型号： | SX1211I084TRT |
| 厂商： | Semtech |
| 文件页数： | 39/92页 |
| 文件大小： | 0K |
| 描述： | IC SNGL-CHIP TXRX 32-TQFN |
| 标准包装： | 1 |
| 频率： | 860 ~ 960MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | AMR，ISM，安防门禁 |
| 功率 - 输出： | 12.5dBm |
| 灵敏度： | -113dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 25mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 584 (CN2011-ZH PDF) |
| 配用： | 1210-1060-2-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-2-ND - 868MHZ ASPICS SX1211 CHIP SET 1210-1060-6-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-6-ND - 868MHZ ASPICS SX1211 CHIP SET 1210-1060-1-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-1-ND - 868MHZ ASPICS SX1211 CHIP SET |
| 其它名称： | SX1211I084DKR |
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SX1211
WIRELESS & SENSING
5.2.2.3. Interrupt Sources and Flags
All interrupt sources and flags are configured in the IRQParam section of the configuration register, with the
exception of Fifo_threshold :
/Fifoempty: /Fifoempty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note
that when retrieving data from the FIFO, /Fifoempty is updated on NSS_DATA falling edge, i.e. when
/Fifoempty is updated to low state the currently started read operation must be completed. In other words,
/Fifoempty state must be checked after each read operation for a decision on the next one (/Fifoempty = 1:
more byte(s) to read; /Fifoempty = 0: no more byte to read).
Write_byte: Write_byte interrupt source goes high for 1 bit period each time a new byte is transferred from the
SR to the FIFO (i.e. each time a new byte is received)
Fifofull: Fifofull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
Fifo_overrun_clr: Fifo_overrun_clr flag is set when a new byte is written by the user (in Tx or Standby modes)
or the SR (in Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1,
note that the FIFO will also be cleared.
Tx_done: Tx_done interrupt source goes high when FIFO is empty and the SR’s last bit has been send to the
modulator (i.e. the last bit of the packet has been sent). One bit period delay is required after the rising edge of
Tx_done to ensure correct RF transmission of the last bit. In practice this may not require special care in the
uC software due to IRQ processing time.
Fifo_threshold: Fifo_threshold interrupt source’s behavior depends on the running mode (Tx, Rx or Stby mode)
and the threshold itself can be programmed via MCParam_Fifo_thresh (B value). This behavior is illustrated in
Figure 32.
IRQ source
1
0
B
B+1 B+2
# of bytes in FIFO
Tx
Rx & Stby
Figure 32: FIFO Threshold IRQ Source Behavior
5.2.2.4. FIFO Clearing
Table 16 below summarizes the status of the FIFO when switching between different modes
Table 16: Status of FIFO when Switching Between Different Modes of the Chip
From
Stby
Stby
Rx
Rx
Tx
Tx
Any
To
Tx
Rx
Tx
Stby
Rx
Stby
Sleep
FIFO Status
Cleared
Not cleared
Cleared
Cleared
Not cleared
Cleared
Not cleared
Cleared
Comments
In Buffered mode, FIFO cannot be written in Stby before Tx
In Packet mode, FIFO can be written in Stby before Tx
In Packet & Buffered modes FIFO can be read in Stby after Rx
Rev 8 – February 2013
Page 39 of 92
www.semtech.com
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