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| 型号： | SX1211I084TRT |
| 厂商： | Semtech |
| 文件页数： | 43/92页 |
| 文件大小： | 0K |
| 描述： | IC SNGL-CHIP TXRX 32-TQFN |
| 标准包装： | 1 |
| 频率： | 860 ~ 960MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | AMR，ISM，安防门禁 |
| 功率 - 输出： | 12.5dBm |
| 灵敏度： | -113dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 25mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 584 (CN2011-ZH PDF) |
| 配用： | 1210-1060-2-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-2-ND - 868MHZ ASPICS SX1211 CHIP SET 1210-1060-6-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-6-ND - 868MHZ ASPICS SX1211 CHIP SET 1210-1060-1-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-1-ND - 868MHZ ASPICS SX1211 CHIP SET |
| 其它名称： | SX1211I084DKR |
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SX1211
WIRELESS & SENSING
5.3.5. uC Connections
SX1211
DATA
IRQ_0
IRQ_1 (DCLK)
NSS_CONFIG
uC
SCK
MOSI
MISO
Figure 37: uC Connections in Continuous Mode
Note that some connections may not be needed depending on the application:
IRQ_0: if Sync and RSSI interrupts are not used. In this case, leave floating.
IRQ_1: if the chip is never used in Tx FSK mode (DCLK connection is not compulsory in Rx and Tx OOK
modes). In this case, leave floating.
MISO: if no read register access is needed. In this case, pull-up to VDD through a 100 k ? resistor.
In addition, NSS_DATA pin (unused in continuous mode) should be pulled-up to VDD through a 100 k ? resistor.
Please refer to Table 13 for SX1211’s pins configuration
5.3.6. Continuous Mode Example
Configure all data processing related registers listed below appropriately. In this example we assume that both
Bit synchronizer and Sync word recognition are on.
Table 19: Relevant Configuration Registers in Continuous Mode (data processing related only)
Tx
Rx
Description
MCParam
Data_mode_x
X
X
Defines data operation mode (
Continuous)
IRQParam
RXParam
SYNCParam
Rx_stby_irq_0
Sync_on
Sync_size
Sync_tol
Sync_value
X
X
X
X
X
Defines IRQ_0 source in Rx mode
Enables Sync word recognition
Defines Sync word size
Defines the error tolerance on Sync word recognition
Defines Sync word value
Tx Mode:
Go to Tx mode (and wait for Tx to be ready, see Figure 50)
Send all packet’s bits on DATA pin synchronously with DCLK signal provided on IRQ_1
Go to Sleep mode
Rx Mode:
Program Rx interrupts: IRQ_0 mapped to Sync (Rx_stby_irq_0=”00”) and IRQ_1 mapped to DCLK (Bit
synchronizer enabled)
Go to Rx mode (note that Rx is not ready immediately, see Figure 49)
Wait for Sync interrupt
Get all packet bits on DATA pin synchronously with DCLK signal provided on IRQ_1
Go to Sleep mode
Rev 8 – February 2013
Page 43 of 92
www.semtech.com
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