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参数资料
| 型号： | SX1211I084TRT |
| 厂商： | Semtech |
| 文件页数： | 44/92页 |
| 文件大小： | 0K |
| 描述： | IC SNGL-CHIP TXRX 32-TQFN |
| 标准包装： | 1 |
| 频率： | 860 ~ 960MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | AMR，ISM，安防门禁 |
| 功率 - 输出： | 12.5dBm |
| 灵敏度： | -113dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 25mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 584 (CN2011-ZH PDF) |
| 配用： | 1210-1060-2-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-2-ND - 868MHZ ASPICS SX1211 CHIP SET 1210-1060-6-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-6-ND - 868MHZ ASPICS SX1211 CHIP SET 1210-1060-1-ND - 915MHZ ASPICS SX1211 CHIP SET 1210-1059-1-ND - 868MHZ ASPICS SX1211 CHIP SET |
| 其它名称： | SX1211I084DKR |
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SX1211
WIRELESS & SENSING
5.4. Buffered Mode
5.4.1. General Description
As illustrated in Figure 38, for Buffered mode operation the NRZ data to (from) the (de)modulator is not directly
accessed by the uC but stored in the FIFO and accessed via the SPI Data interface. This frees the uC for other
tasks between processing data from the SX1211, furthermore it simplifies software development and reduces uC
performance requirements (speed, reactivity). Note that in this mode the packet handler stays inactive.
An important feature is also the ability to empty the FIFO in Stby mode, ensuring low power consumption and
adding greater software flexibility.
SX1211
CONTROL
IRQ_0
IRQ_1
Data
Rx
SYNC
RECOG.
SPI
CONFIG
NSS_CONFIG
FIFO
(+SR)
Tx
DATA
NSS_DATA
SCK
MOSI
MISO
Datapath
Figure 38: Buffered Mode Conceptual View
Note that Bit Synchronizer is automatically enabled in Buffered mode. The Sync word recognition must be enabled
(RXParam_Sync_on=1) independently of the FIFO filling method selected (IRQParam_Fifo_fill_method).
5.4.2. Tx Processing
After entering Tx in Buffered mode, the chip expects the uC to write into the FIFO, via the SPI Data interface, all the
data bytes to be transmitted (preamble, Sync word, payload...).
Actual transmission of first byte will start either when the FIFO is not empty (i.e. first byte written by the uC) or when
the FIFO is full depending on bit IRQParam_Tx_start_irq_0.
In Buffered mode the packet length is not limited, i.e. as long as there are bytes inside the FIFO they are sent.
When the last byte is transferred to the SR, /Fifoempty IRQ source is asserted to warn the uC, at that time FIFO
can still be filled with additional bytes if needed.
When the last bit of the last byte has left the SR (i.e. 8 bit periods later), the Tx_done interrupt source is asserted
and the user can exit Tx mode after waiting at least 1 bit period from the last bit processed by modulator.
Rev 8 – February 2013
Page 44 of 92
www.semtech.com
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