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参数资料
| 型号： | TRC103 |
| 厂商： | RFM |
| 文件页数： | 26/65页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANSCEIVER MULTI-CHANNEL F |
| 标准包装： | 1 |
| 系列： | TRC |
| 频率： | 863MHz ~ 960MHz |
| 数据传输率 - 最大： | 100kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 11dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 4mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-QFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1095-6 |
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A byte transmission can be seen as a rotate operation between the value stored in an 8-bit shift register in the
master device (host microcontroller) and the value stored in an 8-bit shift register in the transceiver. The SCK line
is used to synchronize both SPI bit transfers. Data is transferred full-duplex from master to slave through the SDI
line and from slave to master through the SDO line. The most significant bit is always sent first. In both directions
the rising SCK edge is used to sample a bit, and the falling SCK edge shifts the bits through the shift register.
The active low nSS_CONFIG or nSS_DATA signals are asserted by the master device and should remain low
during a byte transmission. The transmission is synchronized by these nSS_CONFIG or nSS_DATA signals.
While the nSS_CONFIG or nSS_DATA is set to 1, the counters controlling transmission are reset. Reception
starts with the first clock cycle after the falling edge of nSS_CONFIG or nSS_DATA. If either signal goes high dur-
ing a byte transmission the counters are reset and the byte must be retransmitted.
The configuration interface is selected if nSS_CONFIG is low even if the TRC103 is in buffered mode and
nSS_DATA is low (nSS_CONFIG has priority). To configure the transceiver two bytes are required. The first byte
contains a 0 start bit, R/W information (1 = read, 0 = write), 5 bits for the address of the register and a 0 stop bit.
The second byte contains the data to be sent in write mode or the new address to read from in read mode.
S in g le B y te C o n fig u r a tio n R e g is te r W r ite
n S S _ C O N F IG
S C K
S D I
X
S T A R T
R /W
A 4
A 3
A 2
A 1
A 0
S T O P
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
X
R e g is te r A d d r e s s
N e w
R e g is te r V a lu e
S D O
H i-Z
X
X
X
X
X
X
X
X
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
H i-Z
O ld R e g is te r V a lu e
Figure 20
Figure 20 shows the timing diagram for a single byte write sequence to the TRC103 through the SPI configuration
interface. Note that nSS_CONFIG must remain low during the transmission of the two bytes (address and data). If
it goes high after the first byte, then the next byte will be considered as an address byte. When writing more than
one register successively, nSS_CONFIG does not need to have a high-to-low transition between two write se-
quences. The bytes are alternatively considered as an address byte followed by a data byte.
The read sequence through the SPI configuration interface is similar to the write sequence. The host microcon-
troller sends the address during the first SPI communication and then reads the data during a second SPI com-
munication. Note that 0 bits can be input to the SDI during the second SPI communication for a single byte read.
Figure 21 shows the timing diagram for a single byte read sequence from the TRC103 through the SPI.
S in g le B y te C o n fig u r a tio n R e g is te r R e a d
n S S _ C O N F IG
S C K
S D I
X
S T A R T
R /W
A 4
A 3
A 2
A 1
A 0
X
R e g is te r A d d r e s s
S D O
H i-Z
X
X
X
X
X
X
X
X
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
H i-Z
R e g is te r V a lu e
Figure 21
www.RFM.com E-mail: info@rfm.com
? 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 26 of 65
TRC103 - 11/29/12
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