参数资料
型号: TRC103
厂商: RFM
文件页数: 57/65页
文件大小: 0K
描述: RFIC TRANSCEIVER MULTI-CHANNEL F
标准包装: 1
系列: TRC
频率: 863MHz ~ 960MHz
数据传输率 - 最大: 100kbps
调制或协议: FSK,OOK
应用: 通用
功率 - 输出: 11dBm
灵敏度: -112dBm
电源电压: 2.1 V ~ 3.6 V
电流 - 接收: 4mA
电流 - 传输: 30mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-QFN
包装: 标准包装
产品目录页面: 583 (CN2011-ZH PDF)
其它名称: 583-1095-6
8. In transmit mode, IRQ0 will flag when the FIFO is empty.
9. Set IRQCFG0D bit 3 to 1. IRQ1 will flag when the last bit starts to be transmitted.
10. Load the operating frequency into register set MCFG06 - MCFG08 or MCFG09 - MCFG0B.
11. Select the register set to use by setting MCFG00 bit 0. A 0 value selects register set MCFG06 - MCFG08
and a 1 value selects register set MCFG09 - MCFG0B .
12. When ready to transmit, place the TRC103 in synthesizer mode by setting MCFG00 bits 7..5 to 010. Mon-
itor the TRC103 Pin 23 to confirm PLL lock.
13. Place TRC103 in transmit mode by setting MCFG00 bits 7..5 set to 100.
14. Load the message in the FIFO through the SPI port. In Buffered data mode, the transmitted message
must include the 1-0-1-0… training preamble, the start pattern and the data. A length byte at the begin-
ning of the data or a designated end-of-message character is normally used to indicate message length.
15. Monitor IRQ1. It sets when the when the last bit starts to be transmitted. Allow one bit period for the last
bit to be transmitted and then switch to standby mode by setting MCFG00 bits 7..5 to 001.
16. To prepare for receive mode, write a 1 to IRQCFG0E bit 6. This arms the start pattern detection.
17. Switch the TRC103 from standby mode to synthesizer mode by setting MCFG00 bits 7..5 set to 010.
Monitor the TRC103 Pin 23 to confirm PLL lock.
18. Switch from synthesizer mode to receive mode by setting MCFG00 bits 7..5 to 011.
19. Following a start pattern detection, the FIFO will start filling. Note that the preamble and start pattern are
not loaded in the receive FIFO.
20. As each data byte is loaded into the FIFO, IRQ0 will pulse to alert the host microcontroller to retrieve
the byte.
21. The host microcontroller can use a countdown on the length byte or detection of the end-of-message byte
to determine when all of the message data has been retrieved.
22. As soon as all the message has been retrieved, switch the TRC103 to standby mode by setting MCFG00
bits 7..5 to 001.
23. From standby mode, enter another transmit cycle as outlined in steps 12 through 15, or enter another re-
ceive cycle as outlined in steps 16 through 23.
It is possible to transmit messages longer than the FIFO in Buffered data mode by monitoring the nFIFOEMPY
flag and immediately loading additional data bytes. However, messages sent by low power radios such as the
TR103 are normally 127 bytes or less to reduce the chances of corruption due to noise, fading or interference.
6.6.3 Packet Data Mode
The Packet data mode is built on top of the Buffered data mode, and adds a number of standard and optional
features:
?
?
?
Fixed or variable length packet options
Generation of preamble and start pattern (network ID) in transmit mode
DC-balancing of data by scrambling (whitening) or Manchester encoding
www.RFM.com E-mail: info@rfm.com
? 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 57 of 65
TRC103 - 11/29/12
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