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参数资料
| 型号： | TRC103 |
| 厂商： | RFM |
| 文件页数： | 60/65页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANSCEIVER MULTI-CHANNEL F |
| 标准包装： | 1 |
| 系列： | TRC |
| 频率： | 863MHz ~ 960MHz |
| 数据传输率 - 最大： | 100kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 11dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 4mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-QFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1095-6 |
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PKTCFG1E bit 0 is the result of the last CRC calculation. This bit is 1 when the CRC indicates no errors.
PKTCFG1F bit 7 controls CRC packet filtering. If this bit is set to 0, the FIFO is cleared automatically if the CRC
calculation on a received packet indicates an error. If set to 1, the FIFO data is preserved when the CRC calcula-
tion shows an error. PKTCFG1F bit 6 allows the FIFO to be written to or read when the TRC103 is in standby
mode. Setting this bit to 0 allows the FIFO to be written and setting this bit to 1 allows it to be read.
The following is a typical Packet data mode operating scenario. There are many other ways to configure this
flexible data mode.
1. Switch to standby mode by setting MCFG00 bits 7..5 to 001.
2. Set the FIFO to a suitable size for the application in MCFG05 bits 7..6.
3. In PKTCFG1C set bit 7 to 0 to disable Manchester encoding, and set the value in bits 6..0 to match
the FIFO size -1.
4. Load the chosen node address into PKTCFG1D .
5. In PKTCFG1E set bit 7 to 1 to for variable length packets.
6. Set the preamble length in PKTCFG1E bits 6..5.
7. Set bit 4 in PKTCFG1E to 1 to enable DC-balanced scrambling.
8. Set bits 2..1 in PKTCFG1E to 10 to accept packets to this node address and 0x00 broadcasts.
9. Set bit 3 in PKTCFG1E to 1 to enable CRC calculations.
10. In PKTCFG1F set bit 7 to 0 to enable FIFO clear on CRC error.
11. Set the start pattern length in RXCFG12 bits 4..3.
12. Load the start pattern in registers SYNCFG16 up through SYNCFG19 as required.
13. Set IRQCFG0E bit 7 to 0. In receive, the FIFO will start filling when a start pattern is detected.
14. Set IRQCFG0D bit 7..6 to 00. In receive, IRQ0 will flag that a packet has been received with a good CRC
calculation and is ready to retrieve.
15. Set IRQCFG0E bit 4 to 1. In transmit, IRQ0 will clear to 0 when the FIFO is empty (optional).
16. Set IRQCFG0D bit 5..4 to 00. In receive, IRQ1 will signal the CRC is OK (optional).
17. Set IRQCFG0D bit 3 to 1. IRQ1 will flag when the last bit starts to be transmitted.
18. Load the operating frequency into register set MCFG06 - MCFG08 or MCFG09 - MCFG0B.
19. Select the register set to use by setting MCFG00 bit 0. A 0 value selects register set MCFG06 - MCFG08
and a 1 value selects register set MCFG09 - MCFG0B .
20. When ready to transmit, Set bit 6 to 0 in PKTCFG1F to enable FIFO write in standby mode.
21. Load the FIFO with the packet to be transmitted through the SPI port.
22. Place the TRC103 in synthesizer mode by setting MCFG00 bits 7..5 set to 010. Monitor the TRC103 Pin
23 to confirm PLL lock.
www.RFM.com E-mail: info@rfm.com
? 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 60 of 65
TRC103 - 11/29/12
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| TRC104 | 功能描述:射频收发器 Transceiver 2.4 GHz Multi-channel GFSK RoHS:否 制造商:Atmel 频率范围:2322 MHz to 2527 MHz 最大数据速率:2000 Kbps 调制格式:OQPSK 输出功率:4 dBm 类型: 工作电源电压:1.8 V to 3.6 V 最大工作温度:+ 85 C 接口类型:SPI 封装 / 箱体:QFN-32 封装:Tray |
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