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参数资料
| 型号： | TRC103 |
| 厂商： | RFM |
| 文件页数： | 52/65页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANSCEIVER MULTI-CHANNEL F |
| 标准包装： | 1 |
| 系列： | TRC |
| 频率： | 863MHz ~ 960MHz |
| 数据传输率 - 最大： | 100kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 11dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 4mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-QFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1095-6 |
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The dual register set allows a new frequency to be completely entered in one register set while operating on the
other register set. It is important to load all three divider parameters into a register set before switching control to
it. Otherwise, a transient out-of-band frequency shift can occur. The dual register set facilitates FHSS operation,
as the operating frequency for the next hop can be loaded anytime during the current hop interval, making this
programming task less time critical. The values of P, S and R for FSK operation on several common frequencies
are given in Table 65. Software for determining P, S and R values for any in-band frequency is provided with the
TRC103 development kit.
Configuration
MCFG00 bits 4..3
P
S
R
868.3 MHz
10
106
55
133
915.0 MHz
01
100
50
119
955.0 MHz
10
62
50
71
Table 65
6.5 Frequency Synthesizer Channel Programming for OOK Modulation
When using a standard 12.8 MHz reference crystal the RF channel frequency for OOK receive is:
F TXRF = (14.4*(75*(P + 1) + S)/(R + 1)) - F DEV , with P, S in the range 0 to 255, R in the range of 64 to 169
Where F TXRF and transmitter deviation frequency F DEV are in MHz, and P, S, and R are divider integers where S
must be less than (P+1). An F DEV value of 0.1 MHz is normally used, which must match the receiver low IF fre-
quency F IF2 . There are two sets of three registers that hold the values of P, S and R:
Register
MCFG06
MCFG07
MCFG08
MCFG09
MCFG0A
MCFG0B
Divider Parameter
R1
P1
S1
R2
P2
S2
Table 66
MCFG00 bit 0 selects the register set to use for the frequency synthesizer. A 0 value selects register set MCFG06
- MCFG08 and a 1 value selects register set MCFG09 - MCFG0B . In addition, MCFG00 bits 4..3 select the oper-
ating band as follows:
MCFG00 bits 4..3
10
00
01
10
11
Band
863 - 870 MHz
902 - 915 MHz
915 - 928 MHz
950 - 960 MHz
not used
Table 67
The dual register set allows a new frequency to be completely entered in one register set while operating on the
other register set. It is important to load all three divider parameters into a register set before switching control to
it. Otherwise, a transient out-of-band frequency shift can occur. The dual register set facilitates FHSS operation,
as the operating frequency for the next hop can be loaded anytime during the current hop interval, making this
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Page 52 of 65
TRC103 - 11/29/12
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