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参数资料
| 型号： | UPD703111GM-15-UEU |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封装： | 24 X 24 MM, FINE PITCH, PLASTIC, LQFP-176 |
| 文件页数： | 17/238页 |
| 文件大小： | 6598K |
| 代理商： | UPD703111GM-15-UEU |
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CHAPTER 3 CPU FUNCTION
113
Preliminary User’s Manual U16031EJ2V1UD
<3> Transferring program code to internal instruction RAM
Transfer the program code to the internal instruction RAM by program processing or using the DMA
function. When using the DMA function, check the completion of DMA transfer by polling bit 7 (DMAIFn) of
the DMA interrupt control register (DMAICn), without using the DMA transfer end interrupt (INTDMAn) (n = 0
to 3). After transferring the program code, set the internal instruction RAM in the read mode using the
following procedure.
(i)
Set the read mode by using (clearing to 0) the IRAMM0 bit of the internal instruction RAM mode register
(IRAMM). Note that the setting of the IRAMM0 bit must not be changed before it is cleared here.
(ii) After clearing the IRAMM0 bit of the IRAMM register to 0, read the IRAMM0 bit that has been cleared to
0 to confirm that the read mode has been set (to prevent speculative instruction execution by pipeline
operation).
(iii) Branch to the internal instruction RAM area by executing a branch instruction.
Cautions 1. After the reset signal has been cleared, the NMI input is masked by hardware. The NMI
is unmasked as soon as the IRAMM0 bit of the IRAMM register is cleared in step <3> of
the initialization sequence.
2. If it is necessary to confirm NMI input immediately after the reset signal has been
cleared and before the internal instruction RAM is set in the read mode, read the
NMIRS bit of the NMI reset status register (NRS). If this bit is set to 1, it indicates that
the NMI valid edge has been input. Execute the NMI servicing routine as necessary.
The NRS register is used only to check NMI input after the reset signal has been
cleared and before the internal instruction RAM is set in the read mode. This register
is not cleared after the reset signal has been cleared.
3. The software exception and exception trap cannot be masked. Do not execute the
TRAP and DBTRAP instructions until the program code has been transferred to the
internal instruction RAM.
Remarks 1. The NMIRS bit of the NRS register is also set to 1 if an NMI is input after the internal
instruction RAM has been set in the read mode.
In this case, execution automatically
branches to the NMI servicing routine and it is not necessary to confirm the status of the
NMIRS bit.
2. The NMI input mask function is valid after the reset signal has been cleared and before the
internal instruction RAM is set in the read mode.
3. To write data to instruction RAM bank 0 of the internal instruction RAM in the middle of
program execution, set the NP bit of the PSW to 1 to disable NMI and maskable interrupts, so
that the software exception and exception trap do not occur.
Clear the NP bit after the
program has been rewritten, and after it has been confirmed that the IRAMM0 bit of the
IRAMM register has been set to 1 and the read mode has been set.
4. NMI and maskable interrupt requests that are generated while the NP bit of the PSW is set to
1 are held pending. An NMI request is acknowledged immediately after the NP bit has been
cleared to 0. A maskable interrupt is acknowledged immediately after the NP bit has been
cleared to 0 if interrupts are not disabled (DI status) and the interrupt request is not cleared
(by clearing the xxIFn bit of the interrupt control register (xxICn) to 0) before the NP bit is
cleared to 0, and if the xxMKn bit of the interrupt control register is not set to 1. However,
only one of the NMI and maskable interrupt requests is held pending for each interrupt
source, and only one interrupt request is acknowledged even if the same interrupt request is
generated two times or more.
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相关代理商/技术参数 |
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| UPD703114 | 制造商:NEC 制造商全称:NEC 功能描述:32-Bit Single-Chip Microcontrollers |
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