
CHAPTER 3 CPU FUNCTION
79
Preliminary User’s Manual U16031EJ2V1UD
3.4.5
Area
(1) Internal instruction RAM area
(a) Memory map
1 MB of internal instruction RAM area, addresses 00000H to FFFFFH, is reserved. 128 KB are provided
at addresses 000000H to 01FFFFH as physical instruction RAM.
Caution
External memory access cannot be made to addresses 020000H to FFFFFFH. If this
area is accessed, the address bus (A0 to A25) outputs a low level, the data bus (D0 to
D31) goes into a high-impedance state without outputting anything, and the external
bus control signal becomes inactive.
(b) Interrupt/exception table
The V850E/ME2 increases the interrupt response speed by assigning handler addresses corresponding
to interrupts/exceptions.
The collection of these handler addresses is called an interrupt/exception table, which is located in the
internal instruction RAM area. When an interrupt/exception request is acknowledged, execution jumps to
the handler address, and the program written in that memory is executed. Table 3-3 shows the sources
of interrupts/exceptions, and the corresponding addresses.
Table 3-3. Interrupt/Exception Table (1/2)
Start Address of
Interrupt/Exception Table
Interrupt/Exception Source
Start Address of
Interrupt/Exception Table
Interrupt/Exception Source
00100000H
RESET
00000170H
INTPD2
00000010H
NMI0
00000180H
INTPD3
00000040H
TRAP0n (n = 0 to F)
00000190H
INTPD4
00000050H
TRAP1n (n = 0 to F)
000001A0H
INTPD5
00000060H
ILGOP/DBG0
000001B0H
INTPD6
00000080H
INTP10
000001C0H
INTPD7
00000090H
INTP11
000001D0H
INTPD8
000000A0H
INTP21
000001E0H
INTPD9
000000B0H
INTP22
000001F0H
INTPD10
000000C0H
INTP23
00000200H
INTPD11
000000D0H
INTP24
00000210H
INTPD12
000000E0H
INTP25
00000220H
INTPD13
000000F0H
INTP50
00000230H
INTPD14
00000100H
INTP51
00000240H
INTPD15
00000110H
INTP52
00000250H
INTPL0
00000120H
INTP65
00000260H
INTPL1
00000130H
INTP66
00000270H
INTOVC0
00000140H
INTP67
00000280H
INTOVC1
00000150H
INTPD0
00000290H
INTOVC2
00000160H
INTPD1
000002A0H
INTOVC3