
CHAPTER 3 CPU FUNCTION
94
Preliminary User’s Manual U16031EJ2V1UD
(10/26)
Bit Units for Manipulation
Address
Function Register Name
Symbol
R/W
1 Bit
8 Bits 16 Bits
After Reset
FFFFF810H
DMA trigger factor register 0
DTFR0
R/W
√√
00H
FFFFF812H
DMA trigger factor register 1
DTFR1
R/W
√√
00H
FFFFF814H
DMA trigger factor register 2
DTFR2
R/W
√√
00H
FFFFF816H
DMA trigger factor register 3
DTFR3
R/W
√√
00H
FFFFF820H
Power-save mode register
PSMR
R/W
√√
00H
FFFFF822H
Clock control register
CKC
R/W
√
03H
FFFFF824H
Lock register
LOCKR
R
√√
01H
FFFFF82CH
Clock source select register
CKS
R/W
√√
00H
FFFFF82EH
USB clock control register
UCKC
R/W
√√
00H
FFFFF836H
SSCG control register
SSCGC
R/W
√
Note 1
FFFFF8A0H
DMA terminal count output control register
DTOC
R/W
√√
01H
FFFFF8A8H
DMA interface control register
DIFC
R/W
√√
00H
FFFFFA00H
UARTB0 control register 0
UB0CTL0
R/W
√√
10H
FFFFFA02H
UARTB0 control register 2
UB0CTL2
R/W
√
FFFFH
FFFFFA04H
UARTB0 status register
UB0STR
R/W
√√
00H
FFFFFA06H
UARTB0 receive data register AP
Note 2
UB0RXAP
R
√
00FFH
FFFFFA06H
UARTB0 receive data register
UB0RX
R
√
FFH
FFFFFA08H
UARTB0 transmit data register
UB0TX
W
√
FFH
FFFFFA0AH
UARTB0 FIFO control register 0
UB0FIC0
R/W
√√
00H
FFFFFA0BH
UARTB0 FIFO control register 1
UB0FIC1
R/W
√√
00H
FFFFFA0CH
UARTB0 FIFO control register 2
UB0FIC2
R/W
√
0000H
FFFFFA0CH
UARTB0 FIFO control register 2L
UB0FIC2L
R/W
√
00H
FFFFFA0DH
UARTB0 FIFO control register 2H
UB0FIC2H
R/W
√
00H
FFFFFA0EH
UARTB0 FIFO status register 0
UB0FIS0
R
√
00H
FFFFFA0FH
UARTB0 FIFO status register 1
UB0FIS1
R
√
10H
FFFFFA20H
UARTB1 control register 0
UB1CTL0
R/W
√√
10H
FFFFFA22H
UARTB1 control register 2
UB1CTL2
R/W
√
FFFFH
FFFFFA24H
UARTB1 status register
UB1STR
R/W
√√
00H
FFFFFA26H
UARTB1 receive data register AP
Note 2
UB1RXAP
R
√
00FFH
FFFFFA26H
UARTB1 receive data register
UB1RX
R
√
FFH
FFFFFA28H
UARTB1 transmit data register
UB1TX
W
√
FFH
FFFFFA2AH
UARTB1 FIFO control register 0
UB1FIC0
R/W
√√
00H
FFFFFA2BH
UARTB1 FIFO control register 1
UB1FIC1
R/W
√√
00H
Notes 1.
For details, see 8.3.3 SSCG control register (SSCGC).
2.
This register can be used only in FIFO mode.