
CHAPTER 3 CPU FUNCTION
82
Preliminary User’s Manual U16031EJ2V1UD
(3) On-chip peripheral I/O area
4 KB of memory, addresses FFFF000H to FFFFFFFH, are provided as an on-chip peripheral I/O area.
An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFH
Note.
Note
Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O,
specify addresses FFFF000H to FFFFFFFH.
FFFFFFFH
FFFF000H
On-chip peripheral I/O area
(4 KB)
Peripheral I/O registers associated with the operating mode specification and the state monitoring for the on-
chip peripheral I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot be
executed from this area.
Cautions 1. For registers in which byte access is possible, if halfword access is executed, the
higher 8 bits become undefined during a read operation, and the lower 8 bits of data are
written to the register during a write operation.
Do not access an 8-bit register in halfword units.
2. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination
address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the
source/destination address of DMA transfer.
(4) External memory area
256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the
higher 192 MB as data area. The external memory area is addresses x0100000H to xFDFFFFFH.
Access to the external memory area is performed using the chip select signal assigned to each memory block
(which is carried out in the CS unit set by chip area select control registers 0 and 1 (CSC0, CSC1)).
Note that the internal instruction RAM, internal data RAM, and on-chip peripheral I/O areas cannot be used
as external memory areas.