
CHAPTER 2 PIN FUNCTIONS
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Preliminary User’s Manual U16031EJ2V1UD
(8)
PCS0 to PCS7 (Port CS) 3-state I/O
PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when
memory and peripheral I/O are expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CS mode control
register (PMCCS).
(a) Port mode
PCS0 to PCS7 can be set to input or output in 1-bit units using the port CS mode register (PMCS).
(b) Control mode
PCS0 to PCS7 can be set to port/control mode in 1-bit units using the PMCCS register.
(i)
CS0 to CS7 (Chip select) 3-state output
These are the chip select signal output pins for the SRAM, external ROM, external peripheral I/O,
and page ROM area.
The CSn signal is assigned to memory block n (n = 0 to 7).
It becomes active while the bus cycle that accesses the corresponding memory block is activated.
In the idle state (TI), it becomes inactive.
(ii) IOWR (I/O write) 3-state output
This is a write strobe signal output pin for external I/O during DMA flyby transfer.
It indicates
whether the bus cycle currently being executed is a write cycle for external I/O during DMA flyby
transfer, or a write cycle for the SRAM area.
Note that if the IOEN bit of the bus cycle period control register (BCP) is set (1), this signal can be
output even in the normal SRAM, external ROM, or external I/O cycle.
(iii) IORD (I/O read) 3-state output
This is a read strobe signal output pin for external I/O during DMA flyby transfer.
It indicates
whether the bus cycle currently being executed is a read cycle for external I/O during DMA flyby
transfer, or a read cycle for the SRAM area.
Note that if the IOEN bit of the BCP register is set (1), this signal can be output even in the normal
SRAM, external ROM, or external I/O cycle.