参数资料
型号: ADSP-21375KSWZ-2B
厂商: Analog Devices Inc
文件页数: 1/56页
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-MQFP
产品培训模块: SHARC Processor Overview
标准包装: 36
系列: SHARC®
类型: 浮点
接口: DAI,DPI
时钟速率: 266MHz
非易失内存: ROM(256 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-LQFP 裸露焊盘
供应商设备封装: 208-LQFP-EP(28x28)
包装: 托盘
SHARC Processor
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-
DEDICATED AUDIO COMPONENTS
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 33 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in a 208-lead LQFP_EP package
Internal Memory
SIMD Core
Block 0
RAM/ROM
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
Instruction
Cache
5 stage
Sequencer
DAG1/2
Timer
S
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DMD 64-BIT
DMD 64-BIT
PEx
PEy
PMD 64-BIT
Core Bus
Cross Bar
PMD 64-BIT
Internal Memory I/F
FLAGx/IRQx/
TMREXP
JTAG
PERIPHERAL BUS
EPD BUS 48-BIT
IODO 32-BIT
PERIPHERAL BUS
32-BIT
IOD0 BUS
MTM/
DTCP
EP
IOD1
32-BIT
S/PDIF
CORE PCG
FLAGS C-D
TIMER
1-0
TWI
SPI/B
UART
PCG
A-D
IDP/
Tx/Rx PDAP
7-0
SPORT
7-0
CORE
FLAGS
PWM
3-0
AMI
SDRAM
DPI Routing/Pins
DAI Routing/Pins
External Port Pin MUX
DPI Peripherals
DAI Peripherals
Peripherals
External
Port
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 ?2013 Analog Devices, Inc. All rights reserved.
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