参数资料
型号: ADSP-21375KSWZ-2B
厂商: Analog Devices Inc
文件页数: 21/56页
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-MQFP
产品培训模块: SHARC Processor Overview
标准包装: 36
系列: SHARC®
类型: 浮点
接口: DAI,DPI
时钟速率: 266MHz
非易失内存: ROM(256 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-LQFP 裸露焊盘
供应商设备封装: 208-LQFP-EP(28x28)
包装: 托盘
Clock Input
Table 14. Clock Input
200 MHz
266 MHz
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t CK
t CKL
t CKH
t CKRF
t CCLK 2
f VCO
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
30 1
15 1
15 1
5
200
100
45
45
6
10
800
22.5 1
11.25 1
11.25 1
3.75
200
100
45
45
6
10
800
ns
ns
ns
ns
ns
MHz
1
2
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t CCLK .
t CK
CLKIN
t CKH
t CKL
Figure 6. Clock Input
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in Table 9 . Programs can configure the
processor to use its internal clock generator by connecting the
AD S P-21 3 7x
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
CLKIN
C1
22pF
R1
1M *
Y1
XTAL
R2
47 *
C2
22pF
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
16.67 MHz
R2 S HOULD BE CHO S EN TO LIMIT CRY S TAL
DRIVE POWER. REFER TO CRY S TAL
MANUFACTURER’ S S PECIFICATION S
*TYPICAL VALUE S
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
Rev. D | Page 21 of 56 | April 2013
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