参数资料
型号: ADSP-21375KSWZ-2B
厂商: Analog Devices Inc
文件页数: 37/56页
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-MQFP
产品培训模块: SHARC Processor Overview
标准包装: 36
系列: SHARC®
类型: 浮点
接口: DAI,DPI
时钟速率: 266MHz
非易失内存: ROM(256 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-LQFP 裸露焊盘
供应商设备封装: 208-LQFP-EP(28x28)
包装: 托盘
Table 30. Serial Ports—External Late Frame Sync
1.0 V, 200 MHz
1.2 V, 266 MHz
Parameter Min
Max
Min
Max
Unit
Switching Characteristics
t DDTLFSE 1
Data Delay from Late External Transmit Frame Sync
12.7
10
ns
or External Receive Frame Sync with
MCE = 1, MFD = 0
t DDTENFS 1
Data Enable for MCE = 1, MFD = 0 0.5
0.5
ns
1
The t DDTLFSE and t DDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DRIVE
t SFSE/I
SAMPLE
t HFSE/I
DRIVE
DAI_P20–1
(DATA CHANNEL
A/B)
t DDTENFS
1ST BIT
t HDTE/I
t DDTE/I
2ND BIT
t DDTLFSE
LATE EXTERNAL TRANSMIT FS
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DRIVE
t SFSE/I
SAMPLE
t HFSE/I
DRIVE
DAI_P20–1
(DATA CHANNEL
A/B)
t DDTENFS
1ST BIT
t HDTE/I
t DDTE/I
2ND BIT
t DDTLFSE
Figure 22. External Late Frame Sync 1
1
This figure reflects changes made to support left-justified sample pair mode.
Rev. D | Page 37 of 56 | April 2013
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