参数资料
型号: ADSP-21375KSWZ-2B
厂商: Analog Devices Inc
文件页数: 42/56页
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-MQFP
产品培训模块: SHARC Processor Overview
标准包装: 36
系列: SHARC®
类型: 浮点
接口: DAI,DPI
时钟速率: 266MHz
非易失内存: ROM(256 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-LQFP 裸露焊盘
供应商设备封装: 208-LQFP-EP(28x28)
包装: 托盘
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 34 . Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 34. S/PDIF Transmitter Input Data Timing
1.0 V, 200 MHz
1.2 V, 266 MHz
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t SISFS 1
t SIHRS 1
t SISD 1
t SIHD 1
t SITXCLKW
t SITXCLK
t SISCLKW
t SISCLK
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Transmit Clock Width
Transmit Clock Period
Clock Width
Clock Period
3
3
3.2
3
9
20
36
80
3
3
3
3
9
20
36
80
ns
ns
ns
ns
ns
ns
ns
ns
1
The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN
or any of the DAI pins.
t SITXCLK W
SAMPLE EDGE
t SITXCLK
DAI_P20–1
(TxCLK)
t SISCLK
t SISCLKW
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
t SISFS
t SISD
t SIHFS
t SIHD
DAI_P20–1
(SDATA)
Figure 29. S/PDIF Transmitter Input Timing
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 35. Oversampling Clock HFxCLK) Switching Characteristics
Parameter
HFCLK Frequency for HFCLK = 384 × Frame Sync
HFCLK Frequency for HFCLK = 256 × Frame Sync
Frame Rate (FS)
Max
Oversampling Ratio × Frame Sync <= 1/t SITXCLK
49.2
192.0
Rev. D | Page 42 of 56 | April 2013
Unit
MHz
MHz
kHz
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