- 您现在的位置：买卖IC网 > PDF目录19483 > ADSP-21375KSWZ-2B (Analog Devices Inc)IC DSP 32BIT 266MHZ 208-MQFP PDF资料下载
参数资料
| 型号： | ADSP-21375KSWZ-2B |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/56页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 266MHZ 208-MQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 36 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（256 kB） |
| 芯片上RAM： | 64kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-LQFP 裸露焊盘 |
| 供应商设备封装： | 208-LQFP-EP（28x28） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
PIN FUNCTION DESCRIPTIONS
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.
Table 9. Pin Descriptions
State During
and After
Name
ADDR 23–0
DATA 31–0
Type
O/T (pu)
I/O (pu)
Reset
Pulled high/
driven low
Pulled high/
pulled high
Description
External Address. The processor outputs addresses for external memory and periph-
erals on these pins.
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After
reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port
data pins for parallel input data. PDAP over 16-bit external port DATA is not supported
on the ADSP-21375 processor.
DAI _P 20–1
I/O with
programmable
(pu) 1
Pulled high/
pulled high
Digital Applications Interface Pins . These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio-
centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determine the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module
(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled
via the DAI_PIN_PULLUP register.
DPI _P 14–1
I/O with
programmable
(pu) 1
Pulled high/
pulled high
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and general-
purpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP
register.
ACK
I (pu)
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.
RD
WR
SDRAS
SDCAS
SDWE
O/T (pu)
O/T (pu)
O/T (pu)
O/T (pu)
O/T (pu)
Pulled high/
driven high
Pulled high/
driven high
Pulled high/
driven high
Pulled high/
driven high
Pulled high/
External Port Read Enable. RD is asserted whenever the processor reads a word from
external memory. RD has a 22.5 k ? internal pull-up resistor.
External Port Write Enable. WR is asserted when the processor writes a word to
external memory. WR has a 22.5 k ? internal pull-up resistor.
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
driven high
Rev. D | Page 13 of 56 | April 2013
相关PDF资料 |
PDF描述 |
|---|---|
| EEM06DRKH | CONN EDGECARD 12POS DIP .156 SLD |
| SMK316B7682KF-T | CAP CER 6800PF 630V 10% X7R 1206 |
| ECC22DCAH | CONN EDGECARD 44POS R/A .100 SLD |
| XC95144XL-5TQ100C | IC CPLD 144 MCELL 3.3V 100-TQFP |
| VE-20F-CY-F2 | CONVERTER MOD DC/DC 72V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21375KSWZ-2B2 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing |
| ADSP-21375KSWZ-2BX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-21375KSZ-2B | 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT/40-BIT 266MHZ 266MIPS 208MQFP - Trays |
| ADSP-21375KSZ-2BX | 制造商:Analog Devices 功能描述:266 MHZ.PROC W/ON CHIPROM,S/PDIF PBFREE - Trays |
| ADSP-21375KSZ-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
发布紧急采购，3分钟左右您将得到回复。