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参数资料
| 型号： | ADSP-21375KSWZ-2B |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/56页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 266MHZ 208-MQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 36 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（256 kB） |
| 芯片上RAM： | 64kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-LQFP 裸露焊盘 |
| 供应商设备封装： | 208-LQFP-EP（28x28） |
| 包装： | 托盘 |
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Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
? The product of CLKIN and PLLM must never exceed 1/2
f VCO (max) in Table 14 if the input divider is not enabled
(INDIV = 0).
? The product of CLKIN and PLLM must never exceed f VCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
f INPUT = CLKIN when the input divider is disabled or
f INPUT = CLKIN ? 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12 . All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to t PCLK . See the peripheral specific section
for each peripheral’s timing information.
Table 12. Clock Periods
Timing
The VCO frequency is calculated as follows:
f VCO = 2 × PLLM × f INPUT
f CCLK = (2 × PLLM × f INPUT ) ? (2 × PLLD )
where:
Requirements
t CK
t CCLK
t PCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t CCLK
f VCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hard-
ware Reference .
f INPUT = Input frequency to the PLL.
PMCTL
(SDCKR)
PMCTL
PLL
(PLLBP)
XTAL
CLKIN
BUF
CLKIN
DIVIDER
f INPUT
LOOP
FILTER
VCO
f VCO
PLL
DIVIDER
PMCTL
(2xPLLD)
f CCLK
CCLK
SDRAM
DIVIDER
SDCLK
PMCTL
(INDIV)
PLL
MULTIPLIER
PMCTL
(PLLBP)
DIVIDE
BY 2
PCLK
PCLK
CLK_CFGx/PMCTL (2xPLLM)
CCLK
CLKOUT ( TEST ONLY)
RESET
DELAY OF
4096 CLKIN
RESETOUT
BUF
RESETOUT
CYCLES
CORERST
Figure 4. Core Clock and System Clock Relationship to CLKIN
Rev. D | Page 19 of 56 | April 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21375KSWZ-2B2 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing |
| ADSP-21375KSWZ-2BX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-21375KSZ-2B | 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT/40-BIT 266MHZ 266MIPS 208MQFP - Trays |
| ADSP-21375KSZ-2BX | 制造商:Analog Devices 功能描述:266 MHZ.PROC W/ON CHIPROM,S/PDIF PBFREE - Trays |
| ADSP-21375KSZ-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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