参数资料
型号: ADSP-21375KSWZ-2B
厂商: Analog Devices Inc
文件页数: 18/56页
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-MQFP
产品培训模块: SHARC Processor Overview
标准包装: 36
系列: SHARC®
类型: 浮点
接口: DAI,DPI
时钟速率: 266MHz
非易失内存: ROM(256 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-LQFP 裸露焊盘
供应商设备封装: 208-LQFP-EP(28x28)
包装: 托盘
PACKAGE INFORMATION
Table 11. Absolute Maximum Ratings (Continued)
The information presented in Figure 3 provides details about
the package branding for the ADSP-21371/ADSP-21375 proces-
sor. For a complete listing of product availability, see Ordering
Parameter
Load Capacitance
Storage Temperature Range
Junction Temperature under Bias
ESD SENSITIVITY
Rating
200 pF
–65 ? C to +150 ? C
125 ? C
a
ADSP-2137x
tppZ-cc
vvvvvv.x n.n
yyww country_of_origin
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
S
TIMING SPECIFICATIONS
Figure 3. Typical Package Brand
Table 10. Package Brand Information
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
yyww
Field Description
Temperature Range
Package Type
RoHS Compliant Part
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on Page 49 under Test Conditions for voltage refer-
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
MAXIMUM POWER DISSIPATION
See Engineer-to-Engineer Note “Estimating Power Dissipation
for ADSP-2137x SHARC Processors” (EE-318) for detailed ther-
mal and power information regarding maximum power
dissipation. For information on package thermal specifications,
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 11 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 11. Absolute Maximum Ratings
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 4 ). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Parameter
Internal (Core) Supply Voltage (V DDINT )
External (I/O) Supply Voltage (V DDEXT )
Input Voltage –0.5 V to V DDEXT
Output Voltage Swing –0.5 V to V DDEXT
Rating
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+0.5 V
+0.5 V
Rev. D | Page 18 of 56 | April 2013
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